Merge pull request #321 from asudarsa/asudarsa/add_fpga_latency_control_ext
Add support for FPGA latency control extension
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
index 4ed54d4..7e1fe19 100644
--- a/include/spirv/unified1/spirv.bf
+++ b/include/spirv/unified1/spirv.bf
@@ -1149,6 +1149,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
FPGALatencyControlINTEL = 6171,
@@ -1956,6 +1957,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index 1ad517c..dd33af4 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -9044,6 +9044,30 @@
"version" : "None"
},
{
+ "opname" : "OpConvertFToBF16INTEL",
+ "class" : "Conversion",
+ "opcode" : 6116,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Float Value'" }
+ ],
+ "capabilities" : [ "BFloat16ConversionINTEL" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpConvertBF16ToFINTEL",
+ "class" : "Conversion",
+ "opcode" : 6117,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'BFloat16 Value'" }
+ ],
+ "capabilities" : [ "BFloat16ConversionINTEL" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpControlBarrierArriveINTEL",
"class" : "Barrier",
"opcode" : 6142,
@@ -14917,6 +14941,12 @@
"version" : "None"
},
{
+ "enumerant" : "BFloat16ConversionINTEL",
+ "value" : 6115,
+ "extensions" : [ "SPV_INTEL_bfloat16_conversion" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "SplitBarrierINTEL",
"value" : 6141,
"extensions" : [ "SPV_INTEL_split_barrier" ],
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index efae175..fa4cff7 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -1148,6 +1148,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
FPGALatencyControlINTEL = 6171,
@@ -1955,6 +1956,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index ec6d017..9aa359b 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -1148,6 +1148,7 @@
SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
+ SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
SpvCapabilityFPGALatencyControlINTEL = 6171,
@@ -1953,6 +1954,8 @@
SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
+ SpvOpConvertFToBF16INTEL = 6116,
+ SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpGroupIMulKHR = 6401,
@@ -2656,6 +2659,8 @@
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 5b458f7..1f5acda 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -1144,6 +1144,7 @@
CapabilityOptNoneINTEL = 6094,
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
+ CapabilityBFloat16ConversionINTEL = 6115,
CapabilitySplitBarrierINTEL = 6141,
CapabilityFPGAKernelAttributesv2INTEL = 6161,
CapabilityFPGALatencyControlINTEL = 6171,
@@ -1949,6 +1950,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
@@ -2652,6 +2655,8 @@
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index e92920b..42a369a 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -1144,6 +1144,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
FPGALatencyControlINTEL = 6171,
@@ -1949,6 +1950,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
@@ -2652,6 +2655,8 @@
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index f9b9cb2..ef124dc 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -1124,6 +1124,7 @@
"OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114,
+ "BFloat16ConversionINTEL": 6115,
"SplitBarrierINTEL": 6141,
"FPGAKernelAttributesv2INTEL": 6161,
"FPGALatencyControlINTEL": 6171,
@@ -1939,6 +1940,8 @@
"OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091,
"OpSpecConstantCompositeContinuedINTEL": 6092,
+ "OpConvertFToBF16INTEL": 6116,
+ "OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143,
"OpGroupIMulKHR": 6401,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index 1f8ba8e..24699cd 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -1106,6 +1106,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
FPGALatencyControlINTEL = 6171,
@@ -1900,6 +1901,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index 02654ae..69cb94c 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -1106,6 +1106,7 @@
'OptNoneINTEL' : 6094,
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
+ 'BFloat16ConversionINTEL' : 6115,
'SplitBarrierINTEL' : 6141,
'FPGAKernelAttributesv2INTEL' : 6161,
'FPGALatencyControlINTEL' : 6171,
@@ -1900,6 +1901,8 @@
'OpTypeStructContinuedINTEL' : 6090,
'OpConstantCompositeContinuedINTEL' : 6091,
'OpSpecConstantCompositeContinuedINTEL' : 6092,
+ 'OpConvertFToBF16INTEL' : 6116,
+ 'OpConvertBF16ToFINTEL' : 6117,
'OpControlBarrierArriveINTEL' : 6142,
'OpControlBarrierWaitINTEL' : 6143,
'OpGroupIMulKHR' : 6401,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index 485bf36..3b88fc2 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -1151,6 +1151,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
FPGALatencyControlINTEL = 6171,
@@ -1958,6 +1959,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
