Merge pull request #321 from asudarsa/asudarsa/add_fpga_latency_control_ext
Add support for FPGA latency control extension
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
index 39d32fc..7e1fe19 100644
--- a/include/spirv/unified1/spirv.bf
+++ b/include/spirv/unified1/spirv.bf
@@ -576,6 +576,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1150,6 +1152,7 @@
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index ee94b81..dd33af4 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -12551,6 +12551,26 @@
"version" : "None"
},
{
+ "enumerant" : "LatencyControlLabelINTEL",
+ "value" : 6172,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Latency Label'" }
+ ],
+ "capabilities" : [ "FPGALatencyControlINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "LatencyControlConstraintINTEL",
+ "value" : 6173,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Relative To'" },
+ { "kind" : "LiteralInteger", "name" : "'Control Type'" },
+ { "kind" : "LiteralInteger", "name" : "'Relative Cycle'" }
+ ],
+ "capabilities" : [ "FPGALatencyControlINTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "ConduitKernelArgumentINTEL",
"value" : 6175,
"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
@@ -14940,6 +14960,12 @@
"version" : "None"
},
{
+ "enumerant" : "FPGALatencyControlINTEL",
+ "value" : 6171,
+ "extensions" : [ "SPV_INTEL_fpga_latency_control" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPGAArgumentInterfacesINTEL",
"value" : 6174,
"extensions" : [ "SPV_INTEL_fpga_argument_interfaces" ],
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 0ab9c68..fa4cff7 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -575,6 +575,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1149,6 +1151,7 @@
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index 05cbb46..9aa359b 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -581,6 +581,8 @@
SpvDecorationSingleElementVectorINTEL = 6085,
SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
SpvDecorationMediaBlockIOINTEL = 6140,
+ SpvDecorationLatencyControlLabelINTEL = 6172,
+ SpvDecorationLatencyControlConstraintINTEL = 6173,
SpvDecorationConduitKernelArgumentINTEL = 6175,
SpvDecorationRegisterMapKernelArgumentINTEL = 6176,
SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1149,6 +1151,7 @@
SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
+ SpvCapabilityFPGALatencyControlINTEL = 6171,
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMax = 0x7fffffff,
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 0620387..1f5acda 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -577,6 +577,8 @@
DecorationSingleElementVectorINTEL = 6085,
DecorationVectorComputeCallableFunctionINTEL = 6087,
DecorationMediaBlockIOINTEL = 6140,
+ DecorationLatencyControlLabelINTEL = 6172,
+ DecorationLatencyControlConstraintINTEL = 6173,
DecorationConduitKernelArgumentINTEL = 6175,
DecorationRegisterMapKernelArgumentINTEL = 6176,
DecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1145,6 +1147,7 @@
CapabilityBFloat16ConversionINTEL = 6115,
CapabilitySplitBarrierINTEL = 6141,
CapabilityFPGAKernelAttributesv2INTEL = 6161,
+ CapabilityFPGALatencyControlINTEL = 6171,
CapabilityFPGAArgumentInterfacesINTEL = 6174,
CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMax = 0x7fffffff,
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index 12236d0..42a369a 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -577,6 +577,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1145,6 +1147,7 @@
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Max = 0x7fffffff,
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index 5fa3383..ef124dc 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -603,6 +603,8 @@
"SingleElementVectorINTEL": 6085,
"VectorComputeCallableFunctionINTEL": 6087,
"MediaBlockIOINTEL": 6140,
+ "LatencyControlLabelINTEL": 6172,
+ "LatencyControlConstraintINTEL": 6173,
"ConduitKernelArgumentINTEL": 6175,
"RegisterMapKernelArgumentINTEL": 6176,
"MMHostInterfaceAddressWidthINTEL": 6177,
@@ -1125,6 +1127,7 @@
"BFloat16ConversionINTEL": 6115,
"SplitBarrierINTEL": 6141,
"FPGAKernelAttributesv2INTEL": 6161,
+ "FPGALatencyControlINTEL": 6171,
"FPGAArgumentInterfacesINTEL": 6174,
"GroupUniformArithmeticKHR": 6400
}
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index 557ac5e..24699cd 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -550,6 +550,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1107,6 +1109,7 @@
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
},
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index b97bcbb..69cb94c 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -550,6 +550,8 @@
'SingleElementVectorINTEL' : 6085,
'VectorComputeCallableFunctionINTEL' : 6087,
'MediaBlockIOINTEL' : 6140,
+ 'LatencyControlLabelINTEL' : 6172,
+ 'LatencyControlConstraintINTEL' : 6173,
'ConduitKernelArgumentINTEL' : 6175,
'RegisterMapKernelArgumentINTEL' : 6176,
'MMHostInterfaceAddressWidthINTEL' : 6177,
@@ -1107,6 +1109,7 @@
'BFloat16ConversionINTEL' : 6115,
'SplitBarrierINTEL' : 6141,
'FPGAKernelAttributesv2INTEL' : 6161,
+ 'FPGALatencyControlINTEL' : 6171,
'FPGAArgumentInterfacesINTEL' : 6174,
'GroupUniformArithmeticKHR' : 6400,
},
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index 6f542aa..3b88fc2 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -578,6 +578,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1152,6 +1154,7 @@
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
