Merge branch 'dev'
diff --git a/CMakeLists.txt b/CMakeLists.txt index 754d03b..fc56e90 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt
@@ -1,6 +1,6 @@ cmake_minimum_required(VERSION 3.10) -project(xbyak LANGUAGES CXX VERSION 7.39.1) +project(xbyak LANGUAGES CXX VERSION 7.40) file(GLOB headers xbyak/*.h)
diff --git a/doc/changelog.md b/doc/changelog.md index 94a5f23..6190b0e 100644 --- a/doc/changelog.md +++ b/doc/changelog.md
@@ -1,5 +1,6 @@ # History -* 2026/Aug/14 ver 7.39.1 fixed EGPR encoding of vmovq/opCvt3/vpextrw. tmmultf32ps is removed. +* 2026/Aug/15 ver 7.40 support ACE 1.15 +* 2026/Aug/14 ver 7.39.1 fixed EGPR encoding of vmovq/opCvt3/vpextrw. tmmultf32ps is removed. * 2026/Aug/12 ver 7.39 CodeArray: fix reset() to restore write protection. fix a null-pointer write in db() when allocation fails with XBYAK_NO_EXCEPTION.Registers in CodeGenerator (rax, eax, etc.) are now static constexpr members (C++17 or later). StackFrame supports UseSSE(n) / UseAVX(n) / NoVzeroupper * 2026/Aug/03 ver 7.38.0 support pushp/popp. StackFrame supports PUSH2/PPX/APX * 2026/Jul/29 ver 7.37.6 Allocator::alloc rounds up size to a multiple of the page size. improve T_z validation for memory operands
diff --git a/gen/gen_avx512.cpp b/gen/gen_avx512.cpp index e8c75b6..222ad70 100644 --- a/gen/gen_avx512.cpp +++ b/gen/gen_avx512.cpp
@@ -1144,6 +1144,7 @@ printf("void %s(const Zmm& z, const Tmm& t, const Reg32& r) { opVex(z, &r, t, %s, 0x%02X); }\n", t.name, s.c_str(), t.code); } } + // The W1 (load-into-tile) direction of tilemovrow is generated by putTileMov. } void putVmovrs() @@ -1163,6 +1164,214 @@ } } +// ACE 1.15 +void putBsr() +{ + // bsr0 is passed through as a real operand: xed64 requires it visible in the disassembly. + puts("void bsrinit(const Bsr& b) { vex(b, b, 0, T_F2|T_0F38|T_W1, 0x49); setModRM(3, b.getIdx(), 0); }"); + + // T_N1 (no T_N_VL): memory-form disp8N is unscaled, per xed64 decode. + puts("void bsrmovf(const Bsr& b, const Zmm& z1, const Operand& op) { opVex(b, &z1, op, T_MUST_EVEX|T_MAP6|T_EW1|T_N1, 0x95); }"); + + // EVEX.W alone selects load (W1) vs. store (W0); same map/prefix/opcode otherwise. + const struct Tbl { + const char *name; + uint64_t prefix; + } tbl[] = { + { "bsrmovh", T_F2 }, + { "bsrmovl", T_F3 }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& t = tbl[i]; + std::string load = type2String(T_MUST_EVEX|T_MAP6|T_EW1|T_N1|t.prefix); + std::string store = type2String(T_MUST_EVEX|T_MAP6|T_W0|T_N1|t.prefix); + printf("void %s(const Bsr& b, const Operand& op) { opVex(b, 0, op, %s, 0x95); }\n", t.name, load.c_str()); + printf("void %s(const Operand& op, const Bsr& b) { opVex(b, 0, op, %s, 0x95); }\n", t.name, store.c_str()); + } +} + +// Reg-only, load-into-tile direction (zmm row/column -> tile). +// tilemovrow W1 here; its W0 (extract) sibling lives in putAMX_TTRorI with the tcvtrow* family. +// tilemovcol has no extract sibling. +void putTileMov() +{ + const struct Tbl { + const char *name; + uint64_t type; + uint8_t code; + bool imm; + } tbl[] = { + { "tilemovrow", T_66|T_0F3A|T_MUST_EVEX|T_EW1, 0x07, true }, + { "tilemovrow", T_66|T_0F38|T_MUST_EVEX|T_EW1, 0x4A, false }, + { "tilemovcol", T_66|T_0F3A|T_MUST_EVEX|T_EW1, 0x2F, true }, + { "tilemovcol", T_66|T_0F38|T_MUST_EVEX|T_EW1, 0x4B, false }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& t = tbl[i]; + std::string s = type2String(t.type); + if (t.imm) { + printf("void %s(const Tmm& t1, const Zmm& z2, uint8_t imm) { opVex(t1, 0, z2, %s, 0x%02X, imm); }\n", t.name, s.c_str(), t.code); + } else { + printf("void %s(const Tmm& t1, const Zmm& z2, const Reg32& r) { opVex(t1, &r, z2, %s, 0x%02X); }\n", t.name, s.c_str(), t.code); + } + } +} + +void putTop() +{ + // Reg-only; vvvv/rm swap matches tdpbssd. TOP4MX* does not expose bsr0 as an operand (xed64 + // decode shows only tmm1/zmm2/zmm3/imm8), unlike the BSR-family mnemonics above. + const struct Tbl { + const char *name; + uint64_t type; + uint8_t code; + bool imm; + } tbl[] = { + { "top2bf16ps", T_F3|T_0F38|T_MUST_EVEX|T_W0, 0x5C, false }, + { "top4bssd", T_F2|T_0F38|T_MUST_EVEX|T_W0, 0x5E, false }, + { "top4bsud", T_F3|T_0F38|T_MUST_EVEX|T_W0, 0x5E, false }, + { "top4busd", T_66|T_0F38|T_MUST_EVEX|T_W0, 0x5E, false }, + { "top4buud", T_0F38|T_MUST_EVEX|T_W0, 0x5E, false }, + + { "top4mxbf8ps", T_0F3A|T_MUST_EVEX|T_W0, 0x8D, true }, + { "top4mxbhf8ps", T_F2|T_0F3A|T_MUST_EVEX|T_W0, 0x8D, true }, + { "top4mxhbf8ps", T_F3|T_0F3A|T_MUST_EVEX|T_W0, 0x8D, true }, + { "top4mxhf8ps", T_66|T_0F3A|T_MUST_EVEX|T_W0, 0x8D, true }, + { "top4mxbssps", T_F2|T_0F3A|T_MUST_EVEX|T_W0, 0x8F, true }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& t = tbl[i]; + std::string s = type2String(t.type); + if (t.imm) { + printf("void %s(const Tmm& t1, const Zmm& z2, const Zmm& z3, uint8_t imm) { opVex(t1, &z3, z2, %s, 0x%02X, imm); }\n", t.name, s.c_str(), t.code); + } else { + printf("void %s(const Tmm& t1, const Zmm& z2, const Zmm& z3) { opVex(t1, &z3, z2, %s, 0x%02X); }\n", t.name, s.c_str(), t.code); + } + } +} + +void putFp8() +{ + { + const struct Tbl { + const char *name; + uint64_t prefix; + uint8_t code; + } tbl[] = { + { "vcvtps2bf8", T_F3, 0x39 }, + { "vcvtps2bf8s", T_F3, 0x3B }, + { "vcvtps2hf8", T_F3, 0x38 }, + { "vcvtps2hf8s", T_F3, 0x3A }, + { "vcvtrops2hf8", T_66, 0x38 }, + { "vcvtrops2hf8s", T_66, 0x3A }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& p = tbl[i]; + std::string s = type2String(T_MUST_EVEX | T_MAP5 | T_W0 | T_YMM | T_B32 | p.prefix); + printf("void %s(const Xmm& x, const Operand& op) { opCvt5(x, op, %s, 0x%02X); }\n", p.name, s.c_str(), p.code); + } + } + + { + const struct Tbl { + const char *name; + uint8_t code; + } tbl[] = { + { "vcvtbiasps2bf8", 0x39 }, + { "vcvtbiasps2bf8s", 0x3B }, + { "vcvtbiasps2hf8", 0x38 }, + { "vcvtbiasps2hf8s", 0x3A }, + }; + std::string s = type2String(T_MUST_EVEX | T_MAP5 | T_W0 | T_YMM | T_B32); + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& p = tbl[i]; + printf("void %s(const Xmm& x1, const Xmm& x2, const Operand& op) " + "{ opCvt7(x1, x2, op, %s, 0x%02X); }\n", p.name, s.c_str(), p.code); + } + } + + { + const struct Tbl { + const char *name; + uint64_t w; + } tbl[] = { + { "vcvtbf82ps", T_EW1 }, + { "vcvthf82ps", T_W0 }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& p = tbl[i]; + std::string s = type2String(T_MUST_EVEX | T_MAP5 | T_YMM | T_N4 | T_N_VL | p.w); + printf("void %s(const Xmm& x, const Operand& op) " + "{ opVmov(op, x, %s, 0x36, false); }\n", p.name, s.c_str()); + } + } + + { + std::string s = type2String(T_MUST_EVEX | T_MAP5 | T_YMM | T_N8 | T_N_VL | T_W0); + printf("void vcvtbf42hf8(const Xmm& x, const Operand& op) " + "{ opCvt1(x, op, %s, 0x37); }\n", s.c_str()); + } + + { + const struct Tbl { + const char *name; + uint64_t w; + } tbl[] = { + { "vcvtbf62hf8", T_EW1 }, + { "vcvthf62hf8", T_W0 }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& p = tbl[i]; + std::string s = type2String(T_MUST_EVEX | T_MAP5 | T_66 | T_YMM | p.w); + printf("void %s(const Xmm& x, const Xmm& op) { opVex(x, 0, op, %s, 0x37); }\n", p.name, s.c_str()); + } + } + + // ModRM.reg carries the source and ModRM.rm the destination here -- reversed from the plain + // RM shape used by VCVTBF62HF8/VCVTHF62HF8 above, hence opVex(op, 0, x, ...) with x and op + // swapped relative to that call. + { + const struct Tbl { + const char *name; + uint64_t w; + uint8_t code; + } tbl[] = { + { "vcvtbf82bf6s", T_EW1, 0x3E }, + { "vcvthf82hf6s", T_W0, 0x3C }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& p = tbl[i]; + std::string s = type2String(T_MUST_EVEX | T_MAP5 | T_F3 | T_YMM | p.w); + printf("void %s(const Xmm& x, const Xmm& op) { opVex(op, 0, x, %s, 0x%02X); }\n", p.name, s.c_str(), p.code); + } + } + + // vcvt*bf4s: mode=true (dst grows with src, unlike vpmovssdb); T_M_K intentionally + // omitted since that family has no masked-memory-destination form. + { + const struct Tbl { + const char *name; + uint64_t type; + uint8_t code; + bool mode; + } tbl[] = { + { "vcvtbf82bf4s", T_MUST_EVEX | T_MAP5 | T_F3 | T_YMM | T_N8 | T_N_VL | T_EW1, 0x3D, true }, + { "vcvthf82bf4s", T_MUST_EVEX | T_MAP5 | T_F3 | T_YMM | T_N8 | T_N_VL | T_W0, 0x3D, true }, + { "vpmovssdb", T_MUST_EVEX | T_F3 | T_0F38 | T_YMM | T_W0 | T_N4 | T_N_VL | T_M_K, 0x41, false }, + }; + for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { + const Tbl& p = tbl[i]; + std::string s = type2String(p.type); + printf("void %s(const Operand& op, const Xmm& x) { opVmov(op, x, %s, 0x%02X, %s); }\n", p.name, s.c_str(), p.code, p.mode ? "true" : "false"); + } + } + + { + std::string s = type2String(T_MUST_EVEX | T_0F3A | T_YMM | T_W0); + printf("void vunpackb(const Xmm& x, const Operand& op, uint8_t imm) { opAVX_X_XM_IMM(x, op, %s, 0x3D, imm); }\n", s.c_str()); + } +} + int main(int argc, char *[]) { bool only64bit = argc == 2; @@ -1171,6 +1380,11 @@ if (only64bit) { putAMX_TTRorI(); putVmovrs(); + // ACE 1.15 + putBsr(); + putTileMov(); + putTop(); + putFp8(); return 0; } putVcmp();
diff --git a/meson.build b/meson.build index 9c4432d..29522f4 100644 --- a/meson.build +++ b/meson.build
@@ -5,7 +5,7 @@ project( 'xbyak', 'cpp', - version: '7.39.1', + version: '7.40', license: 'BSD-3-Clause', default_options: 'b_ndebug=if-release' )
diff --git a/readme.md b/readme.md index 83b1539..489812a 100644 --- a/readme.md +++ b/readme.md
@@ -1,5 +1,5 @@ -# Xbyak 7.39.1 [![Badge Build]][Build Status] +# Xbyak 7.40 [![Badge Build]][Build Status] *A JIT assembler for x86/x64 architectures supporting advanced instruction sets up to AVX10.2* @@ -32,6 +32,7 @@ ### News +- Support ACE 1.15 - Support AVX10.2 - Support xresldtrk/xsusldtrk - Support RAO-INT for APX @@ -62,10 +63,11 @@ ### References +- [AI Compute Extensions (ACE) Specification](https://x86ecosystem.org/resource/ai-compute-extensions-ace-specification/) - [Intel 64 and IA-32 Architectures Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html) -- [Intel Advanced Performance Extensions (Intel APX) Architecture Specification](https://www.intel.com/content/www/us/en/content-details/836198/intel-advanced-performance-extensions-intel-apx-architecture-specification.html) -- [Intel Advanced Vector Extensions 10.2 (Intel AVX10.2) Architecture Specification](https://www.intel.com/content/www/us/en/content-details/855340/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html) -- [Intel Architecture Instruction Set Extensions Programming Reference](https://www.intel.com/content/www/us/en/content-details/851355/intel-architecture-instruction-set-extensions-programming-reference.html) +- [Intel Advanced Performance Extensions (Intel APX) Architecture Specification](https://www.intel.com/content/www/us/en/content-details/913917/intel-advanced-performance-extensions-intel-apx-architecture-specification.html) +- [Intel Advanced Vector Extensions 10.2 (Intel AVX10.2) Architecture Specification](https://www.intel.com/content/www/us/en/content-details/919693/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html) +- [Intel Architecture Instruction Set Extensions Programming Reference](https://www.intel.com/content/www/us/en/content-details/922690/intel-architecture-instruction-set-extensions-programming-reference.html) - [Intel Software Development Emulator](https://www.intel.com/content/www/us/en/download/684897/intel-software-development-emulator.html) ## License
diff --git a/readme.txt b/readme.txt index 7124824..1c15321 100644 --- a/readme.txt +++ b/readme.txt
@@ -1,5 +1,5 @@ - C++用x86(IA-32), x64(AMD64, x86-64) JITアセンブラ Xbyak 7.39.1 + C++用x86(IA-32), x64(AMD64, x86-64) JITアセンブラ Xbyak 7.40 ----------------------------------------------------------------------------- ◎概要 @@ -404,6 +404,7 @@ ----------------------------------------------------------------------------- ◎履歴 +2026/08/15 ver 7.40 ACE 1.15対応 2026/08/14 ver 7.39.1 vmovq/opCvt3/vpextrwのEGPRエンコード修正. tmmultf32psの削除 2026/08/12 ver 7.39 CodeArrayのreset()時に保護モードを復元. 例外なしモードでnew失敗時にdb()が落ちるバグの修正. CodeGeneratorのレジスタをstatic constexprに変更. StackFrameのUseSSE/UseAVX/NoVzeroupper対応 2026/08/03 ver 7.38.0 pushp/poppサポート StackFrameのPPX/PUSH2/APX対応
diff --git a/sample/cpuid/dmr.txt b/sample/cpuid/dmr.txt index ed124cc..e58b90b 100644 --- a/sample/cpuid/dmr.txt +++ b/sample/cpuid/dmr.txt
@@ -1,2 +1,2 @@ vendor intel - mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp xsave(xgetvb) osxsave pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq avx512_bf16 amx(tile) amx(int8) amx(bf16) avx_vnni avx512_fp16 waitpkg clflushopt cldemote clwb movdiri movdir64b uintr serialize amx_fp16 avx_vnni_int8 avx_ne_convert avx_ifma cmpccxadd prefetchiti sha512 sm3 sm4 avx_vnni_int16 apx_f avx10 amx_fp8 amx_tf32 amx_avx512 amx_movrs movrs amx_complex + mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp xsave(xgetvb) osxsave pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq avx512_bf16 amx(tile) amx(int8) amx(bf16) avx_vnni avx512_fp16 waitpkg clflushopt cldemote clwb movdiri movdir64b uintr serialize amx_fp16 avx_vnni_int8 avx_ne_convert avx_ifma cmpccxadd prefetchiti sha512 sm3 sm4 avx_vnni_int16 apx_f avx10 amx_fp8 amx_tf32 amx_avx512 amx_movrs movrs amx_complex avx10_v1_aux
diff --git a/sample/cpuid/nvl.txt b/sample/cpuid/nvl.txt index 62a767e..28e5b47 100644 --- a/sample/cpuid/nvl.txt +++ b/sample/cpuid/nvl.txt
@@ -1,2 +1,2 @@ vendor intel - mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp xsave(xgetvb) osxsave pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq avx512_bf16 avx_vnni avx512_fp16 waitpkg clflushopt clwb movdiri movdir64b uintr serialize avx_vnni_int8 avx_ne_convert avx_ifma cmpccxadd sha512 sm3 sm4 avx_vnni_int16 apx_f avx10 aeskle wide_kl keylocker keylocker_wide movrs hybrid + mmx mmx2 cmov sse sse2 sse3 ssse3 sse41 sse42 popcnt aesni rdtscp xsave(xgetvb) osxsave pclmulqdq avx fma avx2 bmi1 bmi2 lzcnt prefetchw enh_rep rdrand adx rdseed smap sha f16c movbe avx512f avx512dq avx512_ifma avx512cd avx512bw avx512vl avx512_vbmi avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq avx512_bf16 avx_vnni avx512_fp16 waitpkg clflushopt clwb movdiri movdir64b uintr serialize avx_vnni_int8 avx_ne_convert avx_ifma cmpccxadd sha512 sm3 sm4 avx_vnni_int16 apx_f avx10 aeskle wide_kl keylocker keylocker_wide movrs hybrid avx10_v1_aux
diff --git a/sample/test_util.cpp b/sample/test_util.cpp index 33cc595..ceb22ee 100644 --- a/sample/test_util.cpp +++ b/sample/test_util.cpp
@@ -115,6 +115,9 @@ { Cpu::tMOVRS, "movrs" }, { Cpu::tHYBRID, "hybrid" }, { Cpu::tAMX_COMPLEX, "amx_complex" }, + { Cpu::tACE, "ace" }, + { Cpu::tAVX10_V1_AUX, "avx10_v1_aux" }, + { Cpu::tAVX10_V2_AUX, "avx10_v2_aux" }, }; for (size_t i = 0; i < NUM_OF_ARRAY(tbl); i++) { if (cpu.has(tbl[i].type)) printf(" %s", tbl[i].str); @@ -124,6 +127,9 @@ if (cpu.has(Cpu::tAVX10)) { printf("AVX10 version %d\n", cpu.getAVX10version()); } + if (cpu.has(Cpu::tACE)) { + printf("ACE version %d, max_palette %d\n", cpu.getACEVersion(), cpu.getMaxPalette()); + } if (cpu.has(Cpu::tPOPCNT)) { const int n = 0x12345678; // bitcount = 13 const int ok = 13;
diff --git a/test/Makefile b/test/Makefile index 2787c5e..073bb64 100644 --- a/test/Makefile +++ b/test/Makefile
@@ -27,6 +27,7 @@ ifeq ($(BIT),64) TARGET += jmp64.exe address64.exe apx.exe mmap_allocator.exe TARGET += sf_test.exe cpumask_test.exe + TARGET += ace_1.exe endif all: $(TARGET) @@ -70,8 +71,10 @@ $(CXX) $(CFLAGS) $< -o $@ #-DXBYAK64 cpumask_test.exe: cpumask_test.cpp $(XBYAK_INC) $(CXX) $(CFLAGS) $< -o $@ +ace_1.exe: ace_1.cpp $(XBYAK_INC) + $(CXX) $(CFLAGS) $< -o $@ -TEST_FILES=avx512.txt bf16.txt comp.txt misc.txt convert.txt minmax.txt saturation.txt apx.txt amx.txt avx512old.txt +TEST_FILES=avx512.txt bf16.txt comp.txt misc.txt convert.txt minmax.txt saturation.txt apx.txt amx.txt avx512old.txt ace_1.txt TEST32_FILES=avx512old-32.txt xed_test: detect_x32.exe @set -e; \ @@ -109,6 +112,7 @@ ./apx.exe ./avx10_test.exe ./mmap_allocator.exe + ./ace_1.exe endif test_avx: normalize_prefix.exe
diff --git a/test/ace_1.cpp b/test/ace_1.cpp new file mode 100644 index 0000000..d24945b --- /dev/null +++ b/test/ace_1.cpp
@@ -0,0 +1,39 @@ +#include <stdio.h> +#include <string.h> +#include <xbyak/xbyak.h> +#include <xbyak/xbyak_util.h> +#include <cybozu/test.hpp> + +#ifndef XBYAK64 + #error "only 64-bit mode" +#endif + +using namespace Xbyak; + +// Positive encoding tests for ACE 1.15 are in dataset/ace_1.txt (run by test_by_xed.sh). +// This file keeps only the checks xed cannot cover: operand-guard exceptions. + +// negative tests for the operand guards (opCvt1/opCvt7/opVmov) +CYBOZU_TEST_AUTO(ace_1_bad_combination) +{ + struct Code : Xbyak::CodeGenerator { + Code() + { + // vcvt{bf,hf}82ps : src is xmm or mem regardless of dst width + CYBOZU_TEST_EXCEPTION(vcvtbf82ps(zm1, ym2), std::exception); + CYBOZU_TEST_EXCEPTION(vcvthf82ps(xm1, zm2), std::exception); + // vcvtbf42hf8 : (x|y, x/m), (z, y/m) + CYBOZU_TEST_EXCEPTION(vcvtbf42hf8(zm1, xm2), std::exception); + CYBOZU_TEST_EXCEPTION(vcvtbf42hf8(xm1, ym2), std::exception); + // vcvtbiasps2* : dst is fixed xmm and bias/src widths must match + CYBOZU_TEST_EXCEPTION(vcvtbiasps2bf8(ym1, zm2, zm3), std::exception); + CYBOZU_TEST_EXCEPTION(vcvtbiasps2bf8(xm1, ym2, zm3), std::exception); + CYBOZU_TEST_EXCEPTION(vcvtbiasps2hf8s(xm1, zm2, ym3), std::exception); + // vcvt{bf,hf}82bf4s : (x, x), (x, y), (y, z) only + CYBOZU_TEST_EXCEPTION(vcvtbf82bf4s(ym1, ym2), std::exception); + CYBOZU_TEST_EXCEPTION(vcvthf82bf4s(xm1, zm2), std::exception); + // vpmovssdb : dst is xmm or mem + CYBOZU_TEST_EXCEPTION(vpmovssdb(ym1, ym2), std::exception); + } + } c; +}
diff --git a/test/dataset/ace_1.txt b/test/dataset/ace_1.txt new file mode 100644 index 0000000..40472ac --- /dev/null +++ b/test/dataset/ace_1.txt
@@ -0,0 +1,790 @@ +bsrinit(bsr0); + +bsrmovf(bsr0, zmm0, zmm0); +bsrmovf(bsr0, zmm8, zmm8); +bsrmovf(bsr0, zmm16, zmm16); +bsrmovf(bsr0, zmm24, zmm24); +bsrmovf(bsr0, zmm0, zmm24); +bsrmovf(bsr0, zmm8, zmm16); +bsrmovf(bsr0, zmm16, zmm8); +bsrmovf(bsr0, zmm24, zmm0); +bsrmovf(bsr0, zmm0, zword [rax+rcx*1+0x10]); +bsrmovf(bsr0, zmm8, zword [r8+r9*2+0x20]); +bsrmovf(bsr0, zmm16, zword [r16+r17*4+0x40]); +bsrmovf(bsr0, zmm24, zword [r24+r25*8+0x7f]); + +bsrmovh(bsr0, zmm0); +bsrmovh(bsr0, zmm8); +bsrmovh(bsr0, zmm16); +bsrmovh(bsr0, zmm24); +bsrmovh(zmm0, bsr0); +bsrmovh(zmm8, bsr0); +bsrmovh(zmm16, bsr0); +bsrmovh(zmm24, bsr0); +bsrmovh(bsr0, zword [rax+rcx*1+0x10]); +bsrmovh(bsr0, zword [r8+r9*2+0x20]); +bsrmovh(bsr0, zword [r16+r17*4+0x40]); +bsrmovh(bsr0, zword [r24+r25*8+0x7f]); +bsrmovh(zword [rax+rcx*1+0x10], bsr0); +bsrmovh(zword [r8+r9*2+0x20], bsr0); +bsrmovh(zword [r16+r17*4+0x40], bsr0); +bsrmovh(zword [r24+r25*8+0x7f], bsr0); + +bsrmovl(bsr0, zmm0); +bsrmovl(bsr0, zmm8); +bsrmovl(bsr0, zmm16); +bsrmovl(bsr0, zmm24); +bsrmovl(zmm0, bsr0); +bsrmovl(zmm8, bsr0); +bsrmovl(zmm16, bsr0); +bsrmovl(zmm24, bsr0); +bsrmovl(bsr0, zword [rax+rcx*1+0x08]); +bsrmovl(bsr0, zword [r8+r9*2+0x18]); +bsrmovl(bsr0, zword [r16+r17*4+0x28]); +bsrmovl(bsr0, zword [r24+r25*8+0x38]); +bsrmovl(zword [rax+rcx*1+0x08], bsr0); +bsrmovl(zword [r8+r9*2+0x18], bsr0); +bsrmovl(zword [r16+r17*4+0x28], bsr0); +bsrmovl(zword [r24+r25*8+0x38], bsr0); + +tilemovcol(tmm1, zmm0, eax); +tilemovcol(tmm2, zmm8, r8d); +tilemovcol(tmm3, zmm16, r16d); +tilemovcol(tmm4, zmm24, r24d); +tilemovcol(tmm1, zmm0, r24d); +tilemovcol(tmm2, zmm8, r16d); +tilemovcol(tmm3, zmm16, r8d); +tilemovcol(tmm4, zmm24, eax); +tilemovcol(tmm1, zmm0, 0x00); +tilemovcol(tmm2, zmm8, 0x12); +tilemovcol(tmm3, zmm16, 0x2D); +tilemovcol(tmm4, zmm24, 0x3F); + +tilemovrow(tmm1, zmm0, eax); +tilemovrow(tmm2, zmm8, r8d); +tilemovrow(tmm3, zmm16, r16d); +tilemovrow(tmm4, zmm24, r24d); +tilemovrow(tmm1, zmm0, r24d); +tilemovrow(tmm2, zmm8, r16d); +tilemovrow(tmm3, zmm16, r8d); +tilemovrow(tmm4, zmm24, eax); +tilemovrow(tmm1, zmm0, 0x00); +tilemovrow(tmm2, zmm8, 0x12); +tilemovrow(tmm3, zmm16, 0x2D); +tilemovrow(tmm4, zmm24, 0x3F); + +top2bf16ps(tmm1, zmm0, zmm0); +top2bf16ps(tmm2, zmm8, zmm8); +top2bf16ps(tmm3, zmm16, zmm16); +top2bf16ps(tmm4, zmm24, zmm24); +top2bf16ps(tmm1, zmm0, zmm24); +top2bf16ps(tmm2, zmm8, zmm16); +top2bf16ps(tmm3, zmm16, zmm8); +top2bf16ps(tmm4, zmm24, zmm0); + +top4bssd(tmm1, zmm0, zmm0); +top4bssd(tmm2, zmm8, zmm8); +top4bssd(tmm3, zmm16, zmm16); +top4bssd(tmm4, zmm24, zmm24); +top4bssd(tmm1, zmm0, zmm24); +top4bssd(tmm2, zmm8, zmm16); +top4bssd(tmm3, zmm16, zmm8); +top4bssd(tmm4, zmm24, zmm0); + +top4bsud(tmm1, zmm0, zmm0); +top4bsud(tmm2, zmm8, zmm8); +top4bsud(tmm3, zmm16, zmm16); +top4bsud(tmm4, zmm24, zmm24); +top4bsud(tmm1, zmm0, zmm24); +top4bsud(tmm2, zmm8, zmm16); +top4bsud(tmm3, zmm16, zmm8); +top4bsud(tmm4, zmm24, zmm0); + +top4busd(tmm1, zmm0, zmm0); +top4busd(tmm2, zmm8, zmm8); +top4busd(tmm3, zmm16, zmm16); +top4busd(tmm4, zmm24, zmm24); +top4busd(tmm1, zmm0, zmm24); +top4busd(tmm2, zmm8, zmm16); +top4busd(tmm3, zmm16, zmm8); +top4busd(tmm4, zmm24, zmm0); + +top4buud(tmm1, zmm0, zmm0); +top4buud(tmm2, zmm8, zmm8); +top4buud(tmm3, zmm16, zmm16); +top4buud(tmm4, zmm24, zmm24); +top4buud(tmm1, zmm0, zmm24); +top4buud(tmm2, zmm8, zmm16); +top4buud(tmm3, zmm16, zmm8); +top4buud(tmm4, zmm24, zmm0); + +top4mxbf8ps(tmm1, zmm0, zmm0, 0x00); +top4mxbf8ps(tmm2, zmm8, zmm8, 0x12); +top4mxbf8ps(tmm3, zmm16, zmm16, 0x2D); +top4mxbf8ps(tmm4, zmm24, zmm24, 0x3F); +top4mxbf8ps(tmm1, zmm0, zmm24, 0x3F); +top4mxbf8ps(tmm2, zmm8, zmm16, 0x2D); +top4mxbf8ps(tmm3, zmm16, zmm8, 0x12); +top4mxbf8ps(tmm4, zmm24, zmm0, 0x00); + +top4mxbhf8ps(tmm1, zmm0, zmm0, 0x00); +top4mxbhf8ps(tmm2, zmm8, zmm8, 0x12); +top4mxbhf8ps(tmm3, zmm16, zmm16, 0x2D); +top4mxbhf8ps(tmm4, zmm24, zmm24, 0x3F); +top4mxbhf8ps(tmm1, zmm0, zmm24, 0x3F); +top4mxbhf8ps(tmm2, zmm8, zmm16, 0x2D); +top4mxbhf8ps(tmm3, zmm16, zmm8, 0x12); +top4mxbhf8ps(tmm4, zmm24, zmm0, 0x00); + +top4mxhbf8ps(tmm1, zmm0, zmm0, 0x00); +top4mxhbf8ps(tmm2, zmm8, zmm8, 0x12); +top4mxhbf8ps(tmm3, zmm16, zmm16, 0x2D); +top4mxhbf8ps(tmm4, zmm24, zmm24, 0x3F); +top4mxhbf8ps(tmm1, zmm0, zmm24, 0x3F); +top4mxhbf8ps(tmm2, zmm8, zmm16, 0x2D); +top4mxhbf8ps(tmm3, zmm16, zmm8, 0x12); +top4mxhbf8ps(tmm4, zmm24, zmm0, 0x00); + +top4mxhf8ps(tmm1, zmm0, zmm0, 0x00); +top4mxhf8ps(tmm2, zmm8, zmm8, 0x12); +top4mxhf8ps(tmm3, zmm16, zmm16, 0x2D); +top4mxhf8ps(tmm4, zmm24, zmm24, 0x3F); +top4mxhf8ps(tmm1, zmm0, zmm24, 0x3F); +top4mxhf8ps(tmm2, zmm8, zmm16, 0x2D); +top4mxhf8ps(tmm3, zmm16, zmm8, 0x12); +top4mxhf8ps(tmm4, zmm24, zmm0, 0x00); + +top4mxbssps(tmm1, zmm0, zmm0, 0x00); +top4mxbssps(tmm2, zmm8, zmm8, 0x12); +top4mxbssps(tmm3, zmm16, zmm16, 0x2D); +top4mxbssps(tmm4, zmm24, zmm24, 0x3F); +top4mxbssps(tmm1, zmm0, zmm24, 0x3F); +top4mxbssps(tmm2, zmm8, zmm16, 0x2D); +top4mxbssps(tmm3, zmm16, zmm8, 0x12); +top4mxbssps(tmm4, zmm24, zmm0, 0x00); + +// vcvtps2bf8: opCvt5 shape, dst always xm, src grows xm/ym/zm +vcvtps2bf8(xm0, xm0); +vcvtps2bf8(xm8, xm8); +vcvtps2bf8(xm16, xm16); +vcvtps2bf8(xm24, xm24); +vcvtps2bf8(xm0, xm24); +vcvtps2bf8(xm8, xm16); +vcvtps2bf8(xm16, xm8); +vcvtps2bf8(xm24, xm0); +vcvtps2bf8(xm0, ym0); +vcvtps2bf8(xm8, ym8); +vcvtps2bf8(xm16, ym16); +vcvtps2bf8(xm24, ym24); +vcvtps2bf8(xm0, ym24); +vcvtps2bf8(xm8, ym16); +vcvtps2bf8(xm16, ym8); +vcvtps2bf8(xm24, ym0); +vcvtps2bf8(xm0, zm0); +vcvtps2bf8(xm8, zm8); +vcvtps2bf8(xm16, zm16); +vcvtps2bf8(xm24, zm24); +vcvtps2bf8(xm0, zm24); +vcvtps2bf8(xm8, zm16); +vcvtps2bf8(xm16, zm8); +vcvtps2bf8(xm24, zm0); +vcvtps2bf8(xm0, xword [rax+rcx*1+0x10]); +vcvtps2bf8(xm8, yword [r8+r9*2+0x20]); +vcvtps2bf8(xm16, zword [r16+r17*4+0x40]); +vcvtps2bf8(xm24, zword [r24+r25*8+0x7f]); +vcvtps2bf8(xm0, xword_b [rax+rcx*1+0x10]); +vcvtps2bf8(xm8, yword_b [r8+r9*2+0x20]); +vcvtps2bf8(xm16, zword_b [r16+r17*4+0x40]); +vcvtps2bf8(xm0|k4|T_z, xword [rax+rcx*1+0x10]); +vcvtps2bf8(xm8|k5, zword_b [r8+r9*2+0x40]); +vcvtps2bf8(xm0|k4, xm8); +vcvtps2bf8(xm8|k5, xm16); +vcvtps2bf8(xm16|k6, xm24); +vcvtps2bf8(xm24|k7|T_z, xm0); +vcvtps2bf8(xm0|k4, ym8); +vcvtps2bf8(xm8|k5, ym16); +vcvtps2bf8(xm16|k6, ym24); +vcvtps2bf8(xm24|k7|T_z, ym0); +vcvtps2bf8(xm0|k4, zm8); +vcvtps2bf8(xm8|k5, zm16); +vcvtps2bf8(xm16|k6, zm24); +vcvtps2bf8(xm24|k7|T_z, zm0); + +// vcvtps2bf8s: opCvt5 shape, dst always xm, src grows xm/ym/zm +vcvtps2bf8s(xm0, xm0); +vcvtps2bf8s(xm8, xm8); +vcvtps2bf8s(xm16, xm16); +vcvtps2bf8s(xm24, xm24); +vcvtps2bf8s(xm0, xm24); +vcvtps2bf8s(xm8, xm16); +vcvtps2bf8s(xm16, xm8); +vcvtps2bf8s(xm24, xm0); +vcvtps2bf8s(xm0, ym0); +vcvtps2bf8s(xm8, ym8); +vcvtps2bf8s(xm16, ym16); +vcvtps2bf8s(xm24, ym24); +vcvtps2bf8s(xm0, ym24); +vcvtps2bf8s(xm8, ym16); +vcvtps2bf8s(xm16, ym8); +vcvtps2bf8s(xm24, ym0); +vcvtps2bf8s(xm0, zm0); +vcvtps2bf8s(xm8, zm8); +vcvtps2bf8s(xm16, zm16); +vcvtps2bf8s(xm24, zm24); +vcvtps2bf8s(xm0, zm24); +vcvtps2bf8s(xm8, zm16); +vcvtps2bf8s(xm16, zm8); +vcvtps2bf8s(xm24, zm0); +vcvtps2bf8s(xm0, xword [rax+rcx*1+0x10]); +vcvtps2bf8s(xm8, yword [r8+r9*2+0x20]); +vcvtps2bf8s(xm16, zword [r16+r17*4+0x40]); +vcvtps2bf8s(xm24, zword [r24+r25*8+0x7f]); +vcvtps2bf8s(xm0, xword_b [rax+rcx*1+0x10]); +vcvtps2bf8s(xm8, yword_b [r8+r9*2+0x20]); +vcvtps2bf8s(xm16, zword_b [r16+r17*4+0x40]); +vcvtps2bf8s(xm0|k4|T_z, xword [rax+rcx*1+0x10]); +vcvtps2bf8s(xm8|k5, zword_b [r8+r9*2+0x40]); +vcvtps2bf8s(xm0|k4, xm8); +vcvtps2bf8s(xm8|k5, xm16); +vcvtps2bf8s(xm16|k6, xm24); +vcvtps2bf8s(xm24|k7|T_z, xm0); +vcvtps2bf8s(xm0|k4, ym8); +vcvtps2bf8s(xm8|k5, ym16); +vcvtps2bf8s(xm16|k6, ym24); +vcvtps2bf8s(xm24|k7|T_z, ym0); +vcvtps2bf8s(xm0|k4, zm8); +vcvtps2bf8s(xm8|k5, zm16); +vcvtps2bf8s(xm16|k6, zm24); +vcvtps2bf8s(xm24|k7|T_z, zm0); + +// vcvtps2hf8: opCvt5 shape, dst always xm, src grows xm/ym/zm +vcvtps2hf8(xm0, xm0); +vcvtps2hf8(xm8, xm8); +vcvtps2hf8(xm16, xm16); +vcvtps2hf8(xm24, xm24); +vcvtps2hf8(xm0, xm24); +vcvtps2hf8(xm8, xm16); +vcvtps2hf8(xm16, xm8); +vcvtps2hf8(xm24, xm0); +vcvtps2hf8(xm0, ym0); +vcvtps2hf8(xm8, ym8); +vcvtps2hf8(xm16, ym16); +vcvtps2hf8(xm24, ym24); +vcvtps2hf8(xm0, ym24); +vcvtps2hf8(xm8, ym16); +vcvtps2hf8(xm16, ym8); +vcvtps2hf8(xm24, ym0); +vcvtps2hf8(xm0, zm0); +vcvtps2hf8(xm8, zm8); +vcvtps2hf8(xm16, zm16); +vcvtps2hf8(xm24, zm24); +vcvtps2hf8(xm0, zm24); +vcvtps2hf8(xm8, zm16); +vcvtps2hf8(xm16, zm8); +vcvtps2hf8(xm24, zm0); +vcvtps2hf8(xm0, xword [rax+rcx*1+0x10]); +vcvtps2hf8(xm8, yword [r8+r9*2+0x20]); +vcvtps2hf8(xm16, zword [r16+r17*4+0x40]); +vcvtps2hf8(xm24, zword [r24+r25*8+0x7f]); +vcvtps2hf8(xm0, xword_b [rax+rcx*1+0x10]); +vcvtps2hf8(xm8, yword_b [r8+r9*2+0x20]); +vcvtps2hf8(xm16, zword_b [r16+r17*4+0x40]); +vcvtps2hf8(xm0|k4|T_z, xword [rax+rcx*1+0x10]); +vcvtps2hf8(xm8|k5, zword_b [r8+r9*2+0x40]); +vcvtps2hf8(xm0|k4, xm8); +vcvtps2hf8(xm8|k5, xm16); +vcvtps2hf8(xm16|k6, xm24); +vcvtps2hf8(xm24|k7|T_z, xm0); +vcvtps2hf8(xm0|k4, ym8); +vcvtps2hf8(xm8|k5, ym16); +vcvtps2hf8(xm16|k6, ym24); +vcvtps2hf8(xm24|k7|T_z, ym0); +vcvtps2hf8(xm0|k4, zm8); +vcvtps2hf8(xm8|k5, zm16); +vcvtps2hf8(xm16|k6, zm24); +vcvtps2hf8(xm24|k7|T_z, zm0); + +// vcvtps2hf8s: opCvt5 shape, dst always xm, src grows xm/ym/zm +vcvtps2hf8s(xm0, xm0); +vcvtps2hf8s(xm8, xm8); +vcvtps2hf8s(xm16, xm16); +vcvtps2hf8s(xm24, xm24); +vcvtps2hf8s(xm0, xm24); +vcvtps2hf8s(xm8, xm16); +vcvtps2hf8s(xm16, xm8); +vcvtps2hf8s(xm24, xm0); +vcvtps2hf8s(xm0, ym0); +vcvtps2hf8s(xm8, ym8); +vcvtps2hf8s(xm16, ym16); +vcvtps2hf8s(xm24, ym24); +vcvtps2hf8s(xm0, ym24); +vcvtps2hf8s(xm8, ym16); +vcvtps2hf8s(xm16, ym8); +vcvtps2hf8s(xm24, ym0); +vcvtps2hf8s(xm0, zm0); +vcvtps2hf8s(xm8, zm8); +vcvtps2hf8s(xm16, zm16); +vcvtps2hf8s(xm24, zm24); +vcvtps2hf8s(xm0, zm24); +vcvtps2hf8s(xm8, zm16); +vcvtps2hf8s(xm16, zm8); +vcvtps2hf8s(xm24, zm0); +vcvtps2hf8s(xm0, xword [rax+rcx*1+0x10]); +vcvtps2hf8s(xm8, yword [r8+r9*2+0x20]); +vcvtps2hf8s(xm16, zword [r16+r17*4+0x40]); +vcvtps2hf8s(xm24, zword [r24+r25*8+0x7f]); +vcvtps2hf8s(xm0, xword_b [rax+rcx*1+0x10]); +vcvtps2hf8s(xm8, yword_b [r8+r9*2+0x20]); +vcvtps2hf8s(xm16, zword_b [r16+r17*4+0x40]); +vcvtps2hf8s(xm0|k4|T_z, xword [rax+rcx*1+0x10]); +vcvtps2hf8s(xm8|k5, zword_b [r8+r9*2+0x40]); +vcvtps2hf8s(xm0|k4, xm8); +vcvtps2hf8s(xm8|k5, xm16); +vcvtps2hf8s(xm16|k6, xm24); +vcvtps2hf8s(xm24|k7|T_z, xm0); +vcvtps2hf8s(xm0|k4, ym8); +vcvtps2hf8s(xm8|k5, ym16); +vcvtps2hf8s(xm16|k6, ym24); +vcvtps2hf8s(xm24|k7|T_z, ym0); +vcvtps2hf8s(xm0|k4, zm8); +vcvtps2hf8s(xm8|k5, zm16); +vcvtps2hf8s(xm16|k6, zm24); +vcvtps2hf8s(xm24|k7|T_z, zm0); + +// vcvtrops2hf8: opCvt5 shape, dst always xm, src grows xm/ym/zm +vcvtrops2hf8(xm0, xm0); +vcvtrops2hf8(xm8, xm8); +vcvtrops2hf8(xm16, xm16); +vcvtrops2hf8(xm24, xm24); +vcvtrops2hf8(xm0, xm24); +vcvtrops2hf8(xm8, xm16); +vcvtrops2hf8(xm16, xm8); +vcvtrops2hf8(xm24, xm0); +vcvtrops2hf8(xm0, ym0); +vcvtrops2hf8(xm8, ym8); +vcvtrops2hf8(xm16, ym16); +vcvtrops2hf8(xm24, ym24); +vcvtrops2hf8(xm0, ym24); +vcvtrops2hf8(xm8, ym16); +vcvtrops2hf8(xm16, ym8); +vcvtrops2hf8(xm24, ym0); +vcvtrops2hf8(xm0, zm0); +vcvtrops2hf8(xm8, zm8); +vcvtrops2hf8(xm16, zm16); +vcvtrops2hf8(xm24, zm24); +vcvtrops2hf8(xm0, zm24); +vcvtrops2hf8(xm8, zm16); +vcvtrops2hf8(xm16, zm8); +vcvtrops2hf8(xm24, zm0); +vcvtrops2hf8(xm0, xword [rax+rcx*1+0x10]); +vcvtrops2hf8(xm8, yword [r8+r9*2+0x20]); +vcvtrops2hf8(xm16, zword [r16+r17*4+0x40]); +vcvtrops2hf8(xm24, zword [r24+r25*8+0x7f]); +vcvtrops2hf8(xm0, xword_b [rax+rcx*1+0x10]); +vcvtrops2hf8(xm8, yword_b [r8+r9*2+0x20]); +vcvtrops2hf8(xm16, zword_b [r16+r17*4+0x40]); +vcvtrops2hf8(xm0|k4|T_z, xword [rax+rcx*1+0x10]); +vcvtrops2hf8(xm8|k5, zword_b [r8+r9*2+0x40]); +vcvtrops2hf8(xm0|k4, xm8); +vcvtrops2hf8(xm8|k5, xm16); +vcvtrops2hf8(xm16|k6, xm24); +vcvtrops2hf8(xm24|k7|T_z, xm0); +vcvtrops2hf8(xm0|k4, ym8); +vcvtrops2hf8(xm8|k5, ym16); +vcvtrops2hf8(xm16|k6, ym24); +vcvtrops2hf8(xm24|k7|T_z, ym0); +vcvtrops2hf8(xm0|k4, zm8); +vcvtrops2hf8(xm8|k5, zm16); +vcvtrops2hf8(xm16|k6, zm24); +vcvtrops2hf8(xm24|k7|T_z, zm0); + +// vcvtrops2hf8s: opCvt5 shape, dst always xm, src grows xm/ym/zm +vcvtrops2hf8s(xm0, xm0); +vcvtrops2hf8s(xm8, xm8); +vcvtrops2hf8s(xm16, xm16); +vcvtrops2hf8s(xm24, xm24); +vcvtrops2hf8s(xm0, xm24); +vcvtrops2hf8s(xm8, xm16); +vcvtrops2hf8s(xm16, xm8); +vcvtrops2hf8s(xm24, xm0); +vcvtrops2hf8s(xm0, ym0); +vcvtrops2hf8s(xm8, ym8); +vcvtrops2hf8s(xm16, ym16); +vcvtrops2hf8s(xm24, ym24); +vcvtrops2hf8s(xm0, ym24); +vcvtrops2hf8s(xm8, ym16); +vcvtrops2hf8s(xm16, ym8); +vcvtrops2hf8s(xm24, ym0); +vcvtrops2hf8s(xm0, zm0); +vcvtrops2hf8s(xm8, zm8); +vcvtrops2hf8s(xm16, zm16); +vcvtrops2hf8s(xm24, zm24); +vcvtrops2hf8s(xm0, zm24); +vcvtrops2hf8s(xm8, zm16); +vcvtrops2hf8s(xm16, zm8); +vcvtrops2hf8s(xm24, zm0); +vcvtrops2hf8s(xm0, xword [rax+rcx*1+0x10]); +vcvtrops2hf8s(xm8, yword [r8+r9*2+0x20]); +vcvtrops2hf8s(xm16, zword [r16+r17*4+0x40]); +vcvtrops2hf8s(xm24, zword [r24+r25*8+0x7f]); +vcvtrops2hf8s(xm0, xword_b [rax+rcx*1+0x10]); +vcvtrops2hf8s(xm8, yword_b [r8+r9*2+0x20]); +vcvtrops2hf8s(xm16, zword_b [r16+r17*4+0x40]); +vcvtrops2hf8s(xm0|k4|T_z, xword [rax+rcx*1+0x10]); +vcvtrops2hf8s(xm8|k5, zword_b [r8+r9*2+0x40]); +vcvtrops2hf8s(xm0|k4, xm8); +vcvtrops2hf8s(xm8|k5, xm16); +vcvtrops2hf8s(xm16|k6, xm24); +vcvtrops2hf8s(xm24|k7|T_z, xm0); +vcvtrops2hf8s(xm0|k4, ym8); +vcvtrops2hf8s(xm8|k5, ym16); +vcvtrops2hf8s(xm16|k6, ym24); +vcvtrops2hf8s(xm24|k7|T_z, ym0); +vcvtrops2hf8s(xm0|k4, zm8); +vcvtrops2hf8s(xm8|k5, zm16); +vcvtrops2hf8s(xm16|k6, zm24); +vcvtrops2hf8s(xm24|k7|T_z, zm0); + +// vcvtbiasps2bf8: dst fixed xm, bias/src grow together xm/ym/zm +vcvtbiasps2bf8(xm0, xm0, xm0); +vcvtbiasps2bf8(xm8, xm8, xm8); +vcvtbiasps2bf8(xm16, xm16, xm16); +vcvtbiasps2bf8(xm24, xm24, xm24); +vcvtbiasps2bf8(xm0, ym0, ym0); +vcvtbiasps2bf8(xm8, ym8, ym8); +vcvtbiasps2bf8(xm16, ym16, ym16); +vcvtbiasps2bf8(xm24, ym24, ym24); +vcvtbiasps2bf8(xm0, zm0, zm0); +vcvtbiasps2bf8(xm8, zm8, zm8); +vcvtbiasps2bf8(xm16, zm16, zm16); +vcvtbiasps2bf8(xm24, zm24, zm24); +vcvtbiasps2bf8(xm0, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2bf8(xm8, ym9, yword [r8+r9*2+0x20]); +vcvtbiasps2bf8(xm16, zm17, zword [r16+r17*4+0x40]); +vcvtbiasps2bf8(xm0, xm1, xword_b [rax+rcx*1+0x10]); +vcvtbiasps2bf8(xm8, ym9, yword_b [r8+r9*2+0x20]); +vcvtbiasps2bf8(xm16, zm17, zword_b [r16+r17*4+0x40]); +vcvtbiasps2bf8(xm0|k4|T_z, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2bf8(xm8|k5, zm9, zword_b [r8+r9*2+0x40]); +vcvtbiasps2bf8(xm0|k4, xm8, xm8); +vcvtbiasps2bf8(xm8|k5, xm16, xm16); +vcvtbiasps2bf8(xm16|k6, xm24, xm24); +vcvtbiasps2bf8(xm24|k7|T_z, xm0, xm0); +vcvtbiasps2bf8(xm0|k4, ym8, ym8); +vcvtbiasps2bf8(xm8|k5, ym16, ym16); +vcvtbiasps2bf8(xm16|k6, ym24, ym24); +vcvtbiasps2bf8(xm24|k7|T_z, ym0, ym0); +vcvtbiasps2bf8(xm0|k4, zm8, zm8); +vcvtbiasps2bf8(xm8|k5, zm16, zm16); +vcvtbiasps2bf8(xm16|k6, zm24, zm24); +vcvtbiasps2bf8(xm24|k7|T_z, zm0, zm0); + +// vcvtbiasps2bf8s: dst fixed xm, bias/src grow together xm/ym/zm +vcvtbiasps2bf8s(xm0, xm0, xm0); +vcvtbiasps2bf8s(xm8, xm8, xm8); +vcvtbiasps2bf8s(xm16, xm16, xm16); +vcvtbiasps2bf8s(xm24, xm24, xm24); +vcvtbiasps2bf8s(xm0, ym0, ym0); +vcvtbiasps2bf8s(xm8, ym8, ym8); +vcvtbiasps2bf8s(xm16, ym16, ym16); +vcvtbiasps2bf8s(xm24, ym24, ym24); +vcvtbiasps2bf8s(xm0, zm0, zm0); +vcvtbiasps2bf8s(xm8, zm8, zm8); +vcvtbiasps2bf8s(xm16, zm16, zm16); +vcvtbiasps2bf8s(xm24, zm24, zm24); +vcvtbiasps2bf8s(xm0, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2bf8s(xm8, ym9, yword [r8+r9*2+0x20]); +vcvtbiasps2bf8s(xm16, zm17, zword [r16+r17*4+0x40]); +vcvtbiasps2bf8s(xm0, xm1, xword_b [rax+rcx*1+0x10]); +vcvtbiasps2bf8s(xm8, ym9, yword_b [r8+r9*2+0x20]); +vcvtbiasps2bf8s(xm16, zm17, zword_b [r16+r17*4+0x40]); +vcvtbiasps2bf8s(xm0|k4|T_z, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2bf8s(xm8|k5, zm9, zword_b [r8+r9*2+0x40]); +vcvtbiasps2bf8s(xm0|k4, xm8, xm8); +vcvtbiasps2bf8s(xm8|k5, xm16, xm16); +vcvtbiasps2bf8s(xm16|k6, xm24, xm24); +vcvtbiasps2bf8s(xm24|k7|T_z, xm0, xm0); +vcvtbiasps2bf8s(xm0|k4, ym8, ym8); +vcvtbiasps2bf8s(xm8|k5, ym16, ym16); +vcvtbiasps2bf8s(xm16|k6, ym24, ym24); +vcvtbiasps2bf8s(xm24|k7|T_z, ym0, ym0); +vcvtbiasps2bf8s(xm0|k4, zm8, zm8); +vcvtbiasps2bf8s(xm8|k5, zm16, zm16); +vcvtbiasps2bf8s(xm16|k6, zm24, zm24); +vcvtbiasps2bf8s(xm24|k7|T_z, zm0, zm0); + +// vcvtbiasps2hf8: dst fixed xm, bias/src grow together xm/ym/zm +vcvtbiasps2hf8(xm0, xm0, xm0); +vcvtbiasps2hf8(xm8, xm8, xm8); +vcvtbiasps2hf8(xm16, xm16, xm16); +vcvtbiasps2hf8(xm24, xm24, xm24); +vcvtbiasps2hf8(xm0, ym0, ym0); +vcvtbiasps2hf8(xm8, ym8, ym8); +vcvtbiasps2hf8(xm16, ym16, ym16); +vcvtbiasps2hf8(xm24, ym24, ym24); +vcvtbiasps2hf8(xm0, zm0, zm0); +vcvtbiasps2hf8(xm8, zm8, zm8); +vcvtbiasps2hf8(xm16, zm16, zm16); +vcvtbiasps2hf8(xm24, zm24, zm24); +vcvtbiasps2hf8(xm0, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2hf8(xm8, ym9, yword [r8+r9*2+0x20]); +vcvtbiasps2hf8(xm16, zm17, zword [r16+r17*4+0x40]); +vcvtbiasps2hf8(xm0, xm1, xword_b [rax+rcx*1+0x10]); +vcvtbiasps2hf8(xm8, ym9, yword_b [r8+r9*2+0x20]); +vcvtbiasps2hf8(xm16, zm17, zword_b [r16+r17*4+0x40]); +vcvtbiasps2hf8(xm0|k4|T_z, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2hf8(xm8|k5, zm9, zword_b [r8+r9*2+0x40]); +vcvtbiasps2hf8(xm0|k4, xm8, xm8); +vcvtbiasps2hf8(xm8|k5, xm16, xm16); +vcvtbiasps2hf8(xm16|k6, xm24, xm24); +vcvtbiasps2hf8(xm24|k7|T_z, xm0, xm0); +vcvtbiasps2hf8(xm0|k4, ym8, ym8); +vcvtbiasps2hf8(xm8|k5, ym16, ym16); +vcvtbiasps2hf8(xm16|k6, ym24, ym24); +vcvtbiasps2hf8(xm24|k7|T_z, ym0, ym0); +vcvtbiasps2hf8(xm0|k4, zm8, zm8); +vcvtbiasps2hf8(xm8|k5, zm16, zm16); +vcvtbiasps2hf8(xm16|k6, zm24, zm24); +vcvtbiasps2hf8(xm24|k7|T_z, zm0, zm0); + +// vcvtbiasps2hf8s: dst fixed xm, bias/src grow together xm/ym/zm +vcvtbiasps2hf8s(xm0, xm0, xm0); +vcvtbiasps2hf8s(xm8, xm8, xm8); +vcvtbiasps2hf8s(xm16, xm16, xm16); +vcvtbiasps2hf8s(xm24, xm24, xm24); +vcvtbiasps2hf8s(xm0, ym0, ym0); +vcvtbiasps2hf8s(xm8, ym8, ym8); +vcvtbiasps2hf8s(xm16, ym16, ym16); +vcvtbiasps2hf8s(xm24, ym24, ym24); +vcvtbiasps2hf8s(xm0, zm0, zm0); +vcvtbiasps2hf8s(xm8, zm8, zm8); +vcvtbiasps2hf8s(xm16, zm16, zm16); +vcvtbiasps2hf8s(xm24, zm24, zm24); +vcvtbiasps2hf8s(xm0, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2hf8s(xm8, ym9, yword [r8+r9*2+0x20]); +vcvtbiasps2hf8s(xm16, zm17, zword [r16+r17*4+0x40]); +vcvtbiasps2hf8s(xm0, xm1, xword_b [rax+rcx*1+0x10]); +vcvtbiasps2hf8s(xm8, ym9, yword_b [r8+r9*2+0x20]); +vcvtbiasps2hf8s(xm16, zm17, zword_b [r16+r17*4+0x40]); +vcvtbiasps2hf8s(xm0|k4|T_z, xm1, xword [rax+rcx*1+0x10]); +vcvtbiasps2hf8s(xm8|k5, zm9, zword_b [r8+r9*2+0x40]); +vcvtbiasps2hf8s(xm0|k4, xm8, xm8); +vcvtbiasps2hf8s(xm8|k5, xm16, xm16); +vcvtbiasps2hf8s(xm16|k6, xm24, xm24); +vcvtbiasps2hf8s(xm24|k7|T_z, xm0, xm0); +vcvtbiasps2hf8s(xm0|k4, ym8, ym8); +vcvtbiasps2hf8s(xm8|k5, ym16, ym16); +vcvtbiasps2hf8s(xm16|k6, ym24, ym24); +vcvtbiasps2hf8s(xm24|k7|T_z, ym0, ym0); +vcvtbiasps2hf8s(xm0|k4, zm8, zm8); +vcvtbiasps2hf8s(xm8|k5, zm16, zm16); +vcvtbiasps2hf8s(xm16|k6, zm24, zm24); +vcvtbiasps2hf8s(xm24|k7|T_z, zm0, zm0); + +// vcvtbf82ps: dst grows xm/ym/zm, register-form src fixed xm +vcvtbf82ps(xm0, xm24); +vcvtbf82ps(xm8, xm0); +vcvtbf82ps(xm16, xm8); +vcvtbf82ps(xm24, xm0); +vcvtbf82ps(ym0, xm8); +vcvtbf82ps(ym8, xm16); +vcvtbf82ps(ym16, xm24); +vcvtbf82ps(ym24, xm0); +vcvtbf82ps(zm0, xm16); +vcvtbf82ps(zm8, xm24); +vcvtbf82ps(zm16, xm0); +vcvtbf82ps(zm24, xm8); +vcvtbf82ps(xm0, dword [rax+rcx*1+0x10]); +vcvtbf82ps(ym8, qword [r8+r9*2+0x20]); +vcvtbf82ps(zm16, xword [r16+r17*4+0x40]); +vcvtbf82ps(xm0|k4|T_z, dword [rax+rcx*1+0x10]); +vcvtbf82ps(zm16|k6, xword [r16+r17*4+0x40]); +vcvtbf82ps(xm0|k4, xm8); +vcvtbf82ps(ym8|k5, xm16); +vcvtbf82ps(zm16|k6|T_z, xm24); +vcvtbf82ps(zm24|k7, xm8); + +// vcvthf82ps: dst grows xm/ym/zm, register-form src fixed xm +vcvthf82ps(xm0, xm24); +vcvthf82ps(xm8, xm0); +vcvthf82ps(xm16, xm8); +vcvthf82ps(xm24, xm0); +vcvthf82ps(ym0, xm8); +vcvthf82ps(ym8, xm16); +vcvthf82ps(ym16, xm24); +vcvthf82ps(ym24, xm0); +vcvthf82ps(zm0, xm16); +vcvthf82ps(zm8, xm24); +vcvthf82ps(zm16, xm0); +vcvthf82ps(zm24, xm8); +vcvthf82ps(xm0, dword [rax+rcx*1+0x10]); +vcvthf82ps(ym8, qword [r8+r9*2+0x20]); +vcvthf82ps(zm16, xword [r16+r17*4+0x40]); +vcvthf82ps(xm0|k4|T_z, dword [rax+rcx*1+0x10]); +vcvthf82ps(zm16|k6, xword [r16+r17*4+0x40]); +vcvthf82ps(xm0|k4, xm8); +vcvthf82ps(ym8|k5, xm16); +vcvthf82ps(zm16|k6|T_z, xm24); +vcvthf82ps(zm24|k7, xm8); + +// vcvtbf42hf8: dst grows xm/ym/zm; register src is xm at 128/256, ym at 512 +vcvtbf42hf8(xm0, xm24); +vcvtbf42hf8(xm8, xm0); +vcvtbf42hf8(xm16, xm8); +vcvtbf42hf8(xm24, xm0); +vcvtbf42hf8(ym0, xm8); +vcvtbf42hf8(ym8, xm16); +vcvtbf42hf8(ym16, xm24); +vcvtbf42hf8(ym24, xm0); +vcvtbf42hf8(zm0, ym16); +vcvtbf42hf8(zm8, ym24); +vcvtbf42hf8(zm16, ym0); +vcvtbf42hf8(zm24, ym8); +vcvtbf42hf8(xm0, qword [rax+rcx*1+0x10]); +vcvtbf42hf8(ym8, xword [r8+r9*2+0x20]); +vcvtbf42hf8(zm16, yword [r16+r17*4+0x40]); +vcvtbf42hf8(xm0|k4|T_z, qword [rax+rcx*1+0x10]); +vcvtbf42hf8(zm16|k6, yword [r16+r17*4+0x40]); +vcvtbf42hf8(xm0|k4, xm8); +vcvtbf42hf8(ym8|k5, xm16); +vcvtbf42hf8(zm16|k6|T_z, ym24); +vcvtbf42hf8(zm24|k7, ym0); + +// vcvtbf62hf8: same-VL reinterpret convert, register-only, masking-eligible +vcvtbf62hf8(xm0, xm0); +vcvtbf62hf8(xm8, xm8); +vcvtbf62hf8(xm16, xm16); +vcvtbf62hf8(xm24, xm24); +vcvtbf62hf8(ym0, ym0); +vcvtbf62hf8(ym8, ym8); +vcvtbf62hf8(ym16, ym16); +vcvtbf62hf8(ym24, ym24); +vcvtbf62hf8(zm0, zm0); +vcvtbf62hf8(zm8, zm8); +vcvtbf62hf8(zm16, zm16); +vcvtbf62hf8(zm24, zm24); +vcvtbf62hf8(xm0|k4, xm8); +vcvtbf62hf8(ym8|k5, ym16); +vcvtbf62hf8(zm16|k6|T_z, zm24); +vcvtbf62hf8(zm24|k7, zm16); + +// vcvthf62hf8: same-VL reinterpret convert, register-only, masking-eligible +vcvthf62hf8(xm0, xm0); +vcvthf62hf8(xm8, xm8); +vcvthf62hf8(xm16, xm16); +vcvthf62hf8(xm24, xm24); +vcvthf62hf8(ym0, ym0); +vcvthf62hf8(ym8, ym8); +vcvthf62hf8(ym16, ym16); +vcvthf62hf8(ym24, ym24); +vcvthf62hf8(zm0, zm0); +vcvthf62hf8(zm8, zm8); +vcvthf62hf8(zm16, zm16); +vcvthf62hf8(zm24, zm24); +vcvthf62hf8(xm0|k4, xm8); +vcvthf62hf8(ym8|k5, ym16); +vcvthf62hf8(zm16|k6|T_z, zm24); +vcvthf62hf8(zm24|k7, zm16); + +// vcvtbf82bf6s: same-VL narrowing convert, register-only, no masking form in spec table +vcvtbf82bf6s(xm0, xm0); +vcvtbf82bf6s(xm8, xm8); +vcvtbf82bf6s(xm16, xm16); +vcvtbf82bf6s(xm24, xm24); +vcvtbf82bf6s(ym0, ym0); +vcvtbf82bf6s(ym8, ym8); +vcvtbf82bf6s(ym16, ym16); +vcvtbf82bf6s(ym24, ym24); +vcvtbf82bf6s(zm0, zm0); +vcvtbf82bf6s(zm8, zm8); +vcvtbf82bf6s(zm16, zm16); +vcvtbf82bf6s(zm24, zm24); + +// vcvthf82hf6s: same-VL narrowing convert, register-only, no masking form in spec table +vcvthf82hf6s(xm0, xm0); +vcvthf82hf6s(xm8, xm8); +vcvthf82hf6s(xm16, xm16); +vcvthf82hf6s(xm24, xm24); +vcvthf82hf6s(ym0, ym0); +vcvthf82hf6s(ym8, ym8); +vcvthf82hf6s(ym16, ym16); +vcvthf82hf6s(ym24, ym24); +vcvthf82hf6s(zm0, zm0); +vcvthf82hf6s(zm8, zm8); +vcvthf82hf6s(zm16, zm16); +vcvthf82hf6s(zm24, zm24); + +// vcvtbf82bf4s: narrow-store, dst(mem-or-narrower-reg)/src(wider-reg) grow together +vcvtbf82bf4s(xm0, xm24); +vcvtbf82bf4s(xm8, xm0); +vcvtbf82bf4s(xm16, xm8); +vcvtbf82bf4s(xm24, xm0); +vcvtbf82bf4s(xm0, ym8); +vcvtbf82bf4s(xm8, ym16); +vcvtbf82bf4s(xm16, ym24); +vcvtbf82bf4s(xm24, ym0); +vcvtbf82bf4s(ym0, zm16); +vcvtbf82bf4s(ym8, zm24); +vcvtbf82bf4s(ym16, zm0); +vcvtbf82bf4s(ym24, zm8); +vcvtbf82bf4s(qword [rax+rcx*1+0x10], xm0); +vcvtbf82bf4s(xword [r8+r9*2+0x20], ym8); +vcvtbf82bf4s(yword [r16+r17*4+0x40], zm16); + +// vcvthf82bf4s: narrow-store, dst(mem-or-narrower-reg)/src(wider-reg) grow together +vcvthf82bf4s(xm0, xm24); +vcvthf82bf4s(xm8, xm0); +vcvthf82bf4s(xm16, xm8); +vcvthf82bf4s(xm24, xm0); +vcvthf82bf4s(xm0, ym8); +vcvthf82bf4s(xm8, ym16); +vcvthf82bf4s(xm16, ym24); +vcvthf82bf4s(xm24, ym0); +vcvthf82bf4s(ym0, zm16); +vcvthf82bf4s(ym8, zm24); +vcvthf82bf4s(ym16, zm0); +vcvthf82bf4s(ym24, zm8); +vcvthf82bf4s(qword [rax+rcx*1+0x10], xm0); +vcvthf82bf4s(xword [r8+r9*2+0x20], ym8); +vcvthf82bf4s(yword [r16+r17*4+0x40], zm16); + +// vunpackb: opAVX_X_XM_IMM shape, masking-eligible, all VLs +vunpackb(xm0, xm24, 0x00); +vunpackb(xm8, xm0, 0x08); +vunpackb(xm16, xm8, 0x10); +vunpackb(xm24, xm0, 0x18); +vunpackb(ym0, ym8, 0x00); +vunpackb(ym8, ym16, 0x08); +vunpackb(ym16, ym24, 0x10); +vunpackb(ym24, ym0, 0x18); +vunpackb(zm0, zm16, 0x00); +vunpackb(zm8, zm24, 0x08); +vunpackb(zm16, zm0, 0x10); +vunpackb(zm24, zm8, 0x18); +vunpackb(xm0, xword [rax+rcx*1+0x10], 0x11); +vunpackb(ym8, yword [r8+r9*2+0x20], 0x22); +vunpackb(zm16, zword [r16+r17*4+0x40], 0x33); +vunpackb(xm0|k4, xm8, 0x01); +vunpackb(ym8|k5, ym16, 0x02); +vunpackb(zm16|k6|T_z, zm24, 0x03); +vunpackb(zm24|k7, zm8, 0x04); + +// vpmovssdb: narrow-store, dst register form fixed xm, src grows xm/ym/zm +vpmovssdb(xm0, xm24); +vpmovssdb(xm8, xm0); +vpmovssdb(xm16, xm8); +vpmovssdb(xm24, xm0); +vpmovssdb(xm0, ym8); +vpmovssdb(xm8, ym16); +vpmovssdb(xm16, ym24); +vpmovssdb(xm24, ym0); +vpmovssdb(xm0, zm16); +vpmovssdb(xm8, zm24); +vpmovssdb(xm16, zm0); +vpmovssdb(xm24, zm8); +vpmovssdb(dword [rax+rcx*1+0x10], xm0); +vpmovssdb(qword [r8+r9*2+0x20], ym8); +vpmovssdb(xword [r16+r17*4+0x40], zm16); +vpmovssdb(dword [rax+rcx*1+0x10]|k4, xm0); +vpmovssdb(xword [r16+r17*4+0x40]|k5, zm16); +
diff --git a/test/test_by_xed.py b/test/test_by_xed.py index d216c73..4fd1a12 100644 --- a/test/test_by_xed.py +++ b/test/test_by_xed.py
@@ -8,6 +8,7 @@ tZMM = 3 tMASK = 4 tTMM = 5 +tBSR = 6 g_xmmTbl = ''' xmm0 xmm1 xmm2 xmm3 xmm4 xmm5 xmm6 xmm7 @@ -28,6 +29,10 @@ tmm0 tmm1 tmm2 tmm3 tmm4 tmm5 tmm6 tmm7 '''.split() +g_bsrTbl = ''' +bsr0 +'''.split() + g_regTblStr = ''' eax ecx edx ebx esp ebp esi edi ax cx dx bx sp bp si di @@ -47,7 +52,7 @@ spl bpl sil dil '''.split() -g_regTbl = g_regTblStr.split()+g_ext8bitRegTbl+g_tmmTbl+g_xmmTbl +g_regTbl = g_regTblStr.split()+g_ext8bitRegTbl+g_tmmTbl+g_xmmTbl+g_bsrTbl # name -> position in its line (0-origin) for names without a trailing number g_regIdxTbl = {} @@ -70,7 +75,10 @@ if m: self.idx = int(m.group(1)) self.ext8bit = False - if s[0] == 'k': + if s == 'bsr0': + self.type = tBSR + self.bit = 1024 + elif s[0] == 'k': self.type = tMASK self.bit = 64 elif s[0] == 'r':
diff --git a/test/test_by_xed_all.bat b/test/test_by_xed_all.bat index 9be9f51..71427ea 100644 --- a/test/test_by_xed_all.bat +++ b/test/test_by_xed_all.bat
@@ -1,6 +1,6 @@ @echo off echo 64bit -set TARGETS=avx512.txt bf16.txt misc.txt convert.txt minmax.txt saturation.txt amx.txt apx.txt comp.txt avx512old.txt +set TARGETS=avx512.txt bf16.txt misc.txt convert.txt minmax.txt saturation.txt amx.txt apx.txt comp.txt avx512old.txt ace_1.txt for %%f in (%TARGETS%) do ( echo %%f call test_by_xed.bat dataset\%%f
diff --git a/xbyak/xbyak.h b/xbyak/xbyak.h index d17b03e..2443c5d 100644 --- a/xbyak/xbyak.h +++ b/xbyak/xbyak.h
@@ -507,6 +507,9 @@ F(Tmm, tmm6, 6) \ F(Tmm, tmm7, 7) \ /**/ +#define XBYAK_FOR_EACH_REG_BSR(F) \ + F(Bsr, bsr0, 0) \ + /**/ #define XBYAK_FOR_EACH_REG_RIP(F) \ F(RegRip, rip, 0) \ /**/ @@ -520,6 +523,7 @@ #define XBYAK_FOR_EACH_REG_YMM_EXT(F) #define XBYAK_FOR_EACH_REG_ZMM_EXT(F) #define XBYAK_FOR_EACH_REG_TMM(F) +#define XBYAK_FOR_EACH_REG_BSR(F) #define XBYAK_FOR_EACH_REG_RIP(F) #endif @@ -565,6 +569,7 @@ XBYAK_FOR_EACH_REG_YMM_EXT(F) \ XBYAK_FOR_EACH_REG_ZMM_EXT(F) \ XBYAK_FOR_EACH_REG_TMM(F) \ + XBYAK_FOR_EACH_REG_BSR(F) \ XBYAK_FOR_EACH_REG_RIP(F) \ XBYAK_FOR_EACH_REG_SEGMENT(F) \ /**/ @@ -683,7 +688,7 @@ enum { DEFAULT_MAX_CODE_SIZE = 4096, - VERSION = 0x7391 /* 0xABCD = A.BC(.D) */ + VERSION = 0x7400 /* 0xABCD = A.BC(.D) */ }; #ifndef MIE_INTEGER_TYPE_DEFINED @@ -1107,7 +1112,7 @@ class Operand { static const uint8_t EXT8BIT = 0x20; unsigned int idx_:6; // 0..31 + EXT8BIT = 1 if spl/bpl/sil/dil - unsigned int kind_:10; + unsigned int kind_:11; unsigned int bit_:14; protected: unsigned int zero_:1; @@ -1128,7 +1133,8 @@ ZMM = 1 << 6, OPMASK = 1 << 7, BNDREG = 1 << 8, - TMM = 1 << 9 + TMM = 1 << 9, + BSR = 1 << 10 }; enum Code { #ifdef XBYAK64 @@ -1168,6 +1174,7 @@ XBYAK_CONSTEXPR bool isZMM() const { return is(ZMM); } XBYAK_CONSTEXPR bool isSIMD() const { return is(XMM|YMM|ZMM); } XBYAK_CONSTEXPR bool isTMM() const { return is(TMM); } + XBYAK_CONSTEXPR bool isBSR() const { return is(BSR); } XBYAK_CONSTEXPR bool isXMEM() const { return is(XMM | MEM); } XBYAK_CONSTEXPR bool isYMEM() const { return is(YMM | MEM); } XBYAK_CONSTEXPR bool isZMEM() const { return is(ZMM | MEM); } @@ -1227,6 +1234,7 @@ XBYAK_CONSTEXPR uint32_t getBit() const { return bit_; } const char *toString() const { + if (isBSR()) return "bsr0"; const int idx = getIdx(); if (kind_ == REG) { if (isExt8bit()) { @@ -1425,6 +1433,12 @@ struct Tmm : public Reg { explicit XBYAK_CONSTEXPR Tmm(int idx = 0, Kind kind = Operand::TMM, int bit = 8192) : Reg(idx, kind, bit) { } }; +// Singleton register (idx always 0): 1024-bit width is its true size, but every memory-capable +// mnemonic that uses it sets T_N1 (not T_N_VL), so evex()'s VL==512 disp8N multiplier check is +// never reached with this width. +struct Bsr : public Reg { + explicit XBYAK_CONSTEXPR Bsr(int idx = 0) : Reg(idx, Operand::BSR, 1024) { } +}; #endif struct Opmask : public Reg { @@ -3265,6 +3279,12 @@ } XBYAK_THROW(ERR_BAD_COMBINATION); } + // (x, x, x/m), (x, y, y/m), (x, z, z/m) : dst is fixed XMM regardless of VL + void opCvt7(const Xmm& x1, const Xmm& x2, const Operand& op, uint64_t type, int code) + { + if (!(x1.isXMM() && (op.isMEM() || op.getBit() == x2.getBit()))) XBYAK_THROW(ERR_BAD_COMBINATION) + opVex(x1, &x2, op, type, code); + } const Xmm& cvtIdx0(const Operand& x) const { return x.isZMM() ? zm0 : x.isYMM() ? ym0 : xm0;
diff --git a/xbyak/xbyak_mnemonic.h b/xbyak/xbyak_mnemonic.h index 566a566..f50a7a3 100644 --- a/xbyak/xbyak_mnemonic.h +++ b/xbyak/xbyak_mnemonic.h
@@ -1,4 +1,4 @@ -const char *getVersionString() const { return "7.39.1"; } +const char *getVersionString() const { return "7.40"; } void aadd(const Address& addr, const Reg32e ®) { opMR(addr, reg, T_0F38, 0x0FC, T_APX); } void aand(const Address& addr, const Reg32e ®) { opMR(addr, reg, T_0F38|T_66, 0x0FC, T_APX|T_66); } void adc(const Operand& op, uint32_t imm) { opOI(op, imm, 0x10, 2); } @@ -2663,6 +2663,12 @@ void vucomxsh(const Xmm& x, const Operand& op) { opAVX_X_XM_IMM(x, op, T_N2|T_F3|T_MAP5|T_W0|T_SAE_X|T_MUST_EVEX, 0x2E); } void vucomxss(const Xmm& x, const Operand& op) { opAVX_X_XM_IMM(x, op, T_N4|T_F3|T_0F|T_W0|T_SAE_X|T_MUST_EVEX, 0x2E); } #ifdef XBYAK64 +void bsrinit(const Bsr& b) { vex(b, b, 0, T_F2|T_0F38|T_W1, 0x49); setModRM(3, b.getIdx(), 0); } +void bsrmovf(const Bsr& b, const Zmm& z1, const Operand& op) { opVex(b, &z1, op, T_MUST_EVEX|T_MAP6|T_EW1|T_N1, 0x95); } +void bsrmovh(const Bsr& b, const Operand& op) { opVex(b, 0, op, T_N1|T_F2|T_MAP6|T_EW1|T_MUST_EVEX, 0x95); } +void bsrmovh(const Operand& op, const Bsr& b) { opVex(b, 0, op, T_N1|T_F2|T_MAP6|T_W0|T_MUST_EVEX, 0x95); } +void bsrmovl(const Bsr& b, const Operand& op) { opVex(b, 0, op, T_N1|T_F3|T_MAP6|T_EW1|T_MUST_EVEX, 0x95); } +void bsrmovl(const Operand& op, const Bsr& b) { opVex(b, 0, op, T_N1|T_F3|T_MAP6|T_W0|T_MUST_EVEX, 0x95); } void kmovq(const Reg64& r, const Opmask& k) { opKmov(k, r, true, 64); } void tcvtrowd2ps(const Zmm& z, const Tmm& t, const Reg32& r) { opVex(z, &r, t, T_F3|T_0F38|T_W0|T_MUST_EVEX, 0x4A); } void tcvtrowd2ps(const Zmm& z, const Tmm& t, uint8_t imm) { opVex(z, 0, t, T_F3|T_0F3A|T_W0|T_MUST_EVEX, 0x07, imm); } @@ -2674,12 +2680,47 @@ void tcvtrowps2phh(const Zmm& z, const Tmm& t, uint8_t imm) { opVex(z, 0, t, T_0F3A|T_W0|T_MUST_EVEX, 0x07, imm); } void tcvtrowps2phl(const Zmm& z, const Tmm& t, const Reg32& r) { opVex(z, &r, t, T_66|T_0F38|T_W0|T_MUST_EVEX, 0x6D); } void tcvtrowps2phl(const Zmm& z, const Tmm& t, uint8_t imm) { opVex(z, 0, t, T_F2|T_0F3A|T_W0|T_MUST_EVEX, 0x77, imm); } +void tilemovcol(const Tmm& t1, const Zmm& z2, const Reg32& r) { opVex(t1, &r, z2, T_66|T_0F38|T_EW1|T_MUST_EVEX, 0x4B); } +void tilemovcol(const Tmm& t1, const Zmm& z2, uint8_t imm) { opVex(t1, 0, z2, T_66|T_0F3A|T_EW1|T_MUST_EVEX, 0x2F, imm); } +void tilemovrow(const Tmm& t1, const Zmm& z2, const Reg32& r) { opVex(t1, &r, z2, T_66|T_0F38|T_EW1|T_MUST_EVEX, 0x4A); } +void tilemovrow(const Tmm& t1, const Zmm& z2, uint8_t imm) { opVex(t1, 0, z2, T_66|T_0F3A|T_EW1|T_MUST_EVEX, 0x07, imm); } void tilemovrow(const Zmm& z, const Tmm& t, const Reg32& r) { opVex(z, &r, t, T_66|T_0F38|T_W0|T_MUST_EVEX, 0x4A); } void tilemovrow(const Zmm& z, const Tmm& t, uint8_t imm) { opVex(z, 0, t, T_66|T_0F3A|T_W0|T_MUST_EVEX, 0x07, imm); } +void top2bf16ps(const Tmm& t1, const Zmm& z2, const Zmm& z3) { opVex(t1, &z3, z2, T_F3|T_0F38|T_W0|T_MUST_EVEX, 0x5C); } +void top4bssd(const Tmm& t1, const Zmm& z2, const Zmm& z3) { opVex(t1, &z3, z2, T_F2|T_0F38|T_W0|T_MUST_EVEX, 0x5E); } +void top4bsud(const Tmm& t1, const Zmm& z2, const Zmm& z3) { opVex(t1, &z3, z2, T_F3|T_0F38|T_W0|T_MUST_EVEX, 0x5E); } +void top4busd(const Tmm& t1, const Zmm& z2, const Zmm& z3) { opVex(t1, &z3, z2, T_66|T_0F38|T_W0|T_MUST_EVEX, 0x5E); } +void top4buud(const Tmm& t1, const Zmm& z2, const Zmm& z3) { opVex(t1, &z3, z2, T_0F38|T_W0|T_MUST_EVEX, 0x5E); } +void top4mxbf8ps(const Tmm& t1, const Zmm& z2, const Zmm& z3, uint8_t imm) { opVex(t1, &z3, z2, T_0F3A|T_W0|T_MUST_EVEX, 0x8D, imm); } +void top4mxbhf8ps(const Tmm& t1, const Zmm& z2, const Zmm& z3, uint8_t imm) { opVex(t1, &z3, z2, T_F2|T_0F3A|T_W0|T_MUST_EVEX, 0x8D, imm); } +void top4mxbssps(const Tmm& t1, const Zmm& z2, const Zmm& z3, uint8_t imm) { opVex(t1, &z3, z2, T_F2|T_0F3A|T_W0|T_MUST_EVEX, 0x8F, imm); } +void top4mxhbf8ps(const Tmm& t1, const Zmm& z2, const Zmm& z3, uint8_t imm) { opVex(t1, &z3, z2, T_F3|T_0F3A|T_W0|T_MUST_EVEX, 0x8D, imm); } +void top4mxhf8ps(const Tmm& t1, const Zmm& z2, const Zmm& z3, uint8_t imm) { opVex(t1, &z3, z2, T_66|T_0F3A|T_W0|T_MUST_EVEX, 0x8D, imm); } +void vcvtbf42hf8(const Xmm& x, const Operand& op) { opCvt1(x, op, T_N8|T_N_VL|T_MAP5|T_W0|T_YMM|T_MUST_EVEX, 0x37); } +void vcvtbf62hf8(const Xmm& x, const Xmm& op) { opVex(x, 0, op, T_66|T_MAP5|T_EW1|T_YMM|T_MUST_EVEX, 0x37); } +void vcvtbf82bf4s(const Operand& op, const Xmm& x) { opVmov(op, x, T_N8|T_N_VL|T_F3|T_MAP5|T_EW1|T_YMM|T_MUST_EVEX, 0x3D, true); } +void vcvtbf82bf6s(const Xmm& x, const Xmm& op) { opVex(op, 0, x, T_F3|T_MAP5|T_EW1|T_YMM|T_MUST_EVEX, 0x3E); } +void vcvtbf82ps(const Xmm& x, const Operand& op) { opVmov(op, x, T_N4|T_N_VL|T_MAP5|T_EW1|T_YMM|T_MUST_EVEX, 0x36, false); } +void vcvtbiasps2bf8(const Xmm& x1, const Xmm& x2, const Operand& op) { opCvt7(x1, x2, op, T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x39); } +void vcvtbiasps2bf8s(const Xmm& x1, const Xmm& x2, const Operand& op) { opCvt7(x1, x2, op, T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x3B); } +void vcvtbiasps2hf8(const Xmm& x1, const Xmm& x2, const Operand& op) { opCvt7(x1, x2, op, T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x38); } +void vcvtbiasps2hf8s(const Xmm& x1, const Xmm& x2, const Operand& op) { opCvt7(x1, x2, op, T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x3A); } +void vcvthf62hf8(const Xmm& x, const Xmm& op) { opVex(x, 0, op, T_66|T_MAP5|T_W0|T_YMM|T_MUST_EVEX, 0x37); } +void vcvthf82bf4s(const Operand& op, const Xmm& x) { opVmov(op, x, T_N8|T_N_VL|T_F3|T_MAP5|T_W0|T_YMM|T_MUST_EVEX, 0x3D, true); } +void vcvthf82hf6s(const Xmm& x, const Xmm& op) { opVex(op, 0, x, T_F3|T_MAP5|T_W0|T_YMM|T_MUST_EVEX, 0x3C); } +void vcvthf82ps(const Xmm& x, const Operand& op) { opVmov(op, x, T_N4|T_N_VL|T_MAP5|T_W0|T_YMM|T_MUST_EVEX, 0x36, false); } +void vcvtps2bf8(const Xmm& x, const Operand& op) { opCvt5(x, op, T_F3|T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x39); } +void vcvtps2bf8s(const Xmm& x, const Operand& op) { opCvt5(x, op, T_F3|T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x3B); } +void vcvtps2hf8(const Xmm& x, const Operand& op) { opCvt5(x, op, T_F3|T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x38); } +void vcvtps2hf8s(const Xmm& x, const Operand& op) { opCvt5(x, op, T_F3|T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x3A); } +void vcvtrops2hf8(const Xmm& x, const Operand& op) { opCvt5(x, op, T_66|T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x38); } +void vcvtrops2hf8s(const Xmm& x, const Operand& op) { opCvt5(x, op, T_66|T_MAP5|T_W0|T_YMM|T_MUST_EVEX|T_B32, 0x3A); } void vmovrsb(const Xmm& x, const Address& addr) { opVex(x, 0, addr, T_F2|T_MAP5|T_W0|T_MUST_EVEX, 0x6F); } void vmovrsd(const Xmm& x, const Address& addr) { opVex(x, 0, addr, T_F3|T_MAP5|T_W0|T_MUST_EVEX, 0x6F); } void vmovrsq(const Xmm& x, const Address& addr) { opVex(x, 0, addr, T_F3|T_MAP5|T_EW1|T_MUST_EVEX, 0x6F); } void vmovrsw(const Xmm& x, const Address& addr) { opVex(x, 0, addr, T_F2|T_MAP5|T_EW1|T_MUST_EVEX, 0x6F); } void vpbroadcastq(const Xmm& x, const Reg64& r) { opVex(x, 0, r, T_66|T_0F38|T_EW1|T_YMM|T_MUST_EVEX, 0x7C); } +void vpmovssdb(const Operand& op, const Xmm& x) { opVmov(op, x, T_N4|T_N_VL|T_F3|T_0F38|T_W0|T_YMM|T_MUST_EVEX|T_M_K, 0x41, false); } +void vunpackb(const Xmm& x, const Operand& op, uint8_t imm) { opAVX_X_XM_IMM(x, op, T_0F3A|T_W0|T_YMM|T_MUST_EVEX, 0x3D, imm); } #endif #endif
diff --git a/xbyak/xbyak_util.h b/xbyak/xbyak_util.h index cb97edf..95722f3 100644 --- a/xbyak/xbyak_util.h +++ b/xbyak/xbyak_util.h
@@ -179,6 +179,8 @@ uint32_t coresSharingDataCache_[maxNumberCacheLevels]; uint32_t dataCacheLevels_; uint32_t avx10version_; + uint32_t aceVersion_; + uint32_t maxPalette_; uint32_t get32bitAsBE(const char *x) const { @@ -590,6 +592,9 @@ XBYAK_DEFINE_TYPE(96, tMOVRS); XBYAK_DEFINE_TYPE(97, tHYBRID); XBYAK_DEFINE_TYPE(98, tAMX_COMPLEX); + XBYAK_DEFINE_TYPE(99, tACE); + XBYAK_DEFINE_TYPE(100, tAVX10_V1_AUX); + XBYAK_DEFINE_TYPE(101, tAVX10_V2_AUX); #undef XBYAK_SPLIT_ID #undef XBYAK_DEFINE_TYPE @@ -601,6 +606,8 @@ , coresSharingDataCache_() , dataCacheLevels_(0) , avx10version_(0) + , aceVersion_(0) + , maxPalette_(0) { uint32_t data[4] = {}; const uint32_t& eax = data[0]; @@ -748,6 +755,7 @@ if (edx & (1U << 14)) type_ |= tPREFETCHITI; if (edx & (1U << 19)) type_ |= tAVX10; if (edx & (1U << 21)) type_ |= tAPX_F; + if (ecx & (1U << 11)) type_ |= tACE; } if (maxNum >= 0x1e) { getCpuidEx(0x1e, 0, data); @@ -770,7 +778,21 @@ } if (has(tAVX10) && maxNum >= 0x24) { getCpuidEx(0x24, 0, data); + const uint32_t maxNumSubLeaves = eax; avx10version_ = ebx & mask(7); + if (maxNumSubLeaves >= 1) { + getCpuidEx(0x24, 1, data); + if (ecx & (1U << 2)) type_ |= tAVX10_V1_AUX; + if (ecx & (1U << 3)) type_ |= tAVX10_V2_AUX; + } + } + if (has(tAMX_TILE) && maxNum >= 0x1d) { + getCpuidEx(0x1d, 0, data); + maxPalette_ = eax; + if (has(tACE) && maxPalette_ >= 2) { + getCpuidEx(0x1d, 2, data); + aceVersion_ = eax & mask(8); + } } setFamily(); setNumCores(); @@ -789,6 +811,8 @@ return (type & type_) == type; } int getAVX10version() const { return avx10version_; } + int getACEVersion() const { return aceVersion_; } + int getMaxPalette() const { return maxPalette_; } }; #ifdef _MSC_VER #pragma warning(pop)