add mpx
diff --git a/gen/gen_code.cpp b/gen/gen_code.cpp
index 7de2259..d298b2d 100644
--- a/gen/gen_code.cpp
+++ b/gen/gen_code.cpp
@@ -937,6 +937,17 @@
printf("void %s(const Reg& reg, const Operand& op) { opMovxx(reg, op, 0x%02X); }\n", p->name, p->code);
}
}
+ // mpx
+ {
+ puts("void bndcl(const BoundsReg& bnd, const Operand& op) { db(0xF3); opR_ModM(op, i32e, bnd.getIdx(), 0x0F, 0x1A, NONE, !op.isMEM()); }");
+ puts("void bndcu(const BoundsReg& bnd, const Operand& op) { db(0xF2); opR_ModM(op, i32e, bnd.getIdx(), 0x0F, 0x1A, NONE, !op.isMEM()); }");
+ puts("void bndcn(const BoundsReg& bnd, const Operand& op) { db(0xF2); opR_ModM(op, i32e, bnd.getIdx(), 0x0F, 0x1B, NONE, !op.isMEM()); }");
+ puts("void bndldx(const BoundsReg& bnd, const Address& addr) { opModM(addr, bnd, 0x0F, 0x1A); }");
+ puts("void bndmk(const BoundsReg& bnd, const Address& addr) { db(0xF3); opModM(addr, bnd, 0x0F, 0x1B); }");
+ puts("void bndmov(const BoundsReg& bnd, const Operand& op) { db(0x66); opModRM(bnd, op, op.isBNDREG(), op.isMEM(), 0x0F, 0x1A); }");
+ puts("void bndmov(const Address& addr, const BoundsReg& bnd) { db(0x66); opModM(addr, bnd, 0x0F, 0x1B); }");
+ puts("void bndstx(const Address& addr, const BoundsReg& bnd) { opModM(addr, bnd, 0x0F, 0x1B); }");
+ }
// misc
{
puts("void lea(const Reg& reg, const Address& addr) { if (!reg.isBit(16 | i32e)) throw Error(ERR_BAD_SIZE_OF_REGISTER); opModM(addr, reg, 0x8D); }");
diff --git a/readme.md b/readme.md
index f096ed9..3ef08e5 100644
--- a/readme.md
+++ b/readme.md
@@ -333,6 +333,7 @@
History
-------------
+* 2017/Aug/08 ver 5.50 add mpx(thanks to magurosan)
* 2017/Aug/08 ver 5.45 add sha(thanks to magurosan)
* 2017/Aug/08 ver 5.44 add prefetchw(thanks to rsdubtso)
* 2017/Jul/12 ver 5.432 reduce warnings of PVS studio
diff --git a/sample/test_util.cpp b/sample/test_util.cpp
index ea04a06..d349787 100644
--- a/sample/test_util.cpp
+++ b/sample/test_util.cpp
@@ -54,7 +54,8 @@
{ Cpu::tSMAP, "smap" },
{ Cpu::tHLE, "hle" },
{ Cpu::tRTM, "rtm" },
- { Cpu::tRTM, "sha" },
+ { Cpu::tMPX, "mpx" },
+ { Cpu::tSHA, "sha" },
{ Cpu::tPREFETCHWT1, "prefetchwt1" },
{ Cpu::tF16C, "f16c" },
{ Cpu::tMOVBE, "movbe" },
diff --git a/test/make_nm.cpp b/test/make_nm.cpp
index 9f9a40a..6eff1e5 100644
--- a/test/make_nm.cpp
+++ b/test/make_nm.cpp
@@ -112,6 +112,7 @@
const uint64 M_xword = 1ULL << 61;
const uint64 M_yword = 1ULL << 62;
const uint64 MY_1to4 = 1ULL << 18;
+const uint64 BNDREG = 1ULL << 22;
const uint64 NOPARA = 1ULL << (bitEnd - 1);
@@ -402,6 +403,13 @@
}
case K2:
return isXbyak_ ? "k3 | k5" : "k3{k5}";
+ case BNDREG:
+ {
+ static const char tbl[][5] = {
+ "bnd0", "bnd1", "bnd2", "bnd3",
+ };
+ return tbl[idx % 4];
+ }
#ifdef XBYAK64
case XMM_SAE:
return isXbyak_ ? "xmm25 | T_sae" : "xmm25, {sae}";
@@ -1341,6 +1349,21 @@
put("sha256msg1", XMM, XMM|MEM);
put("sha256msg2", XMM, XMM|MEM);
}
+ void putMPX() const
+ {
+#ifdef XBYAK64
+ const uint64 reg = REG64;
+#else
+ const uint64 reg = REG32;
+#endif
+ put("bndcl", BNDREG, reg|MEM);
+ put("bndcu", BNDREG, reg|MEM);
+ put("bndcn", BNDREG, reg|MEM);
+ put("bndldx", BNDREG, MEM);
+ put("bndmk", BNDREG, MEM);
+ put("bndmov", BNDREG, BNDREG|MEM);
+ put("bndstx", MEM, BNDREG);
+ }
void putFpuMem16_32() const
{
const char tbl[][8] = {
@@ -2380,6 +2403,7 @@
putFpu();
putFpuFpu();
putCmp();
+ putMPX();
#endif
#ifdef XBYAK64
diff --git a/test/nm_frame.cpp b/test/nm_frame.cpp
index 8903746..95240c7 100644
--- a/test/nm_frame.cpp
+++ b/test/nm_frame.cpp
@@ -31,6 +31,10 @@
int main()
try
{
+ size_t size = sizeof(Xbyak::Operand);
+ if (size != 4) {
+ printf("sizeof Operand %d\n", (int)size);
+ }
try {
Sample s;
s.gen();
diff --git a/xbyak/xbyak.h b/xbyak/xbyak.h
index 1522daa..d993620 100644
--- a/xbyak/xbyak.h
+++ b/xbyak/xbyak.h
@@ -105,7 +105,7 @@
enum {
DEFAULT_MAX_CODE_SIZE = 4096,
- VERSION = 0x5450 /* 0xABCD = A.BC(D) */
+ VERSION = 0x5500 /* 0xABCD = A.BC(D) */
};
#ifndef MIE_INTEGER_TYPE_DEFINED
@@ -365,7 +365,8 @@
XMM = 1 << 4,
YMM = 1 << 5,
ZMM = 1 << 6,
- OPMASK = 1 << 7
+ OPMASK = 1 << 7,
+ BNDREG = 1 << 8,
};
enum Code {
#ifdef XBYAK64
@@ -382,7 +383,7 @@
Operand() : idx_(0), kind_(0), bit_(0), zero_(0), mask_(0), rounding_(0) { }
Operand(int idx, Kind kind, int bit, bool ext8bit = 0)
: idx_(static_cast<uint8>(idx | (ext8bit ? EXT8BIT : 0)))
- , kind_(static_cast<uint8>(kind))
+ , kind_(kind)
, bit_(bit)
, zero_(0), mask_(0), rounding_(0)
{
@@ -399,6 +400,7 @@
bool isYMEM() const { return is(YMM | MEM); }
bool isZMEM() const { return is(ZMM | MEM); }
bool isOPMASK() const { return is(OPMASK); }
+ bool isBNDREG() const { return is(BNDREG); }
bool isREG(int bit = 0) const { return is(REG, bit); }
bool isMEM(int bit = 0) const { return is(MEM, bit); }
bool isFPU() const { return is(FPU); }
@@ -486,6 +488,9 @@
} else if (isFPU()) {
static const char *tbl[8] = { "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7" };
return tbl[idx];
+ } else if (isBNDREG()) {
+ static const char *tbl[4] = { "bnd0", "bnd1", "bnd2", "bnd3" };
+ return tbl[idx];
}
throw Error(ERR_INTERNAL);
}
@@ -565,6 +570,10 @@
explicit Opmask(int idx = 0) : Reg(idx, Operand::OPMASK, 64) {}
};
+struct BoundsReg : public Reg {
+ explicit BoundsReg(int idx = 0) : Reg(idx, Operand::BNDREG, 128) {}
+};
+
template<class T>T operator|(const T& x, const Opmask& k) { T r(x); r.setOpmaskIdx(k.getIdx()); return r; }
template<class T>T operator|(const T& x, const EvexModifierZero&) { T r(x); r.setZero(); return r; }
template<class T>T operator|(const T& x, const EvexModifierRounding& emr) { T r(x); r.setRounding(emr.rounding); return r; }
@@ -2039,6 +2048,7 @@
const AddressFrame ptr_b, xword_b, yword_b, zword_b; // broadcast such as {1to2}, {1to4}, {1to8}, {1to16}, {b}
const Fpu st0, st1, st2, st3, st4, st5, st6, st7;
const Opmask k0, k1, k2, k3, k4, k5, k6, k7;
+ const BoundsReg bnd0, bnd1, bnd2, bnd3;
const EvexModifierRounding T_sae, T_rn_sae, T_rd_sae, T_ru_sae, T_rz_sae; // {sae}, {rn-sae}, {rd-sae}, {ru-sae}, {rz-sae}
const EvexModifierZero T_z; // {z}
#ifdef XBYAK64
@@ -2313,6 +2323,7 @@
, ptr_b(0, true), xword_b(128, true), yword_b(256, true), zword_b(512, true)
, st0(0), st1(1), st2(2), st3(3), st4(4), st5(5), st6(6), st7(7)
, k0(0), k1(1), k2(2), k3(3), k4(4), k5(5), k6(6), k7(7)
+ , bnd0(0), bnd1(1), bnd2(2), bnd3(3)
, T_sae(T_SAE), T_rn_sae(T_RN_SAE), T_rd_sae(T_RD_SAE), T_ru_sae(T_RU_SAE), T_rz_sae(T_RZ_SAE)
, T_z()
#ifdef XBYAK64
@@ -2400,6 +2411,7 @@
static const AddressFrame ptr(0), byte(8), word(16), dword(32), qword(64);
static const Fpu st0(0), st1(1), st2(2), st3(3), st4(4), st5(5), st6(6), st7(7);
static const Opmask k0(0), k1(1), k2(2), k3(3), k4(4), k5(5), k6(6), k7(7);
+static const BoundsReg bnd0(0), bnd1(1), bnd2(2), bnd3(3);
#ifdef XBYAK64
static const Reg64 rax(Operand::RAX), rcx(Operand::RCX), rdx(Operand::RDX), rbx(Operand::RBX), rsp(Operand::RSP), rbp(Operand::RBP), rsi(Operand::RSI), rdi(Operand::RDI), r8(Operand::R8), r9(Operand::R9), r10(Operand::R10), r11(Operand::R11), r12(Operand::R12), r13(Operand::R13), r14(Operand::R14), r15(Operand::R15);
static const Reg32 r8d(8), r9d(9), r10d(10), r11d(11), r12d(12), r13d(13), r14d(14), r15d(15);
diff --git a/xbyak/xbyak_mnemonic.h b/xbyak/xbyak_mnemonic.h
index b2495f6..34c6b68 100644
--- a/xbyak/xbyak_mnemonic.h
+++ b/xbyak/xbyak_mnemonic.h
@@ -1,4 +1,4 @@
-const char *getVersionString() const { return "5.45"; }
+const char *getVersionString() const { return "5.50"; }
void adc(const Operand& op, uint32 imm) { opRM_I(op, imm, 0x10, 2); }
void adc(const Operand& op1, const Operand& op2) { opRM_RM(op1, op2, 0x10); }
void adcx(const Reg32e& reg, const Operand& op) { opGen(reg, op, 0xF6, 0x66, isREG32_REG32orMEM, NONE, 0x38); }
@@ -32,6 +32,14 @@
void blsi(const Reg32e& r, const Operand& op) { opGpr(Reg32e(3, r.getBit()), op, r, T_0F38, 0xf3, false); }
void blsmsk(const Reg32e& r, const Operand& op) { opGpr(Reg32e(2, r.getBit()), op, r, T_0F38, 0xf3, false); }
void blsr(const Reg32e& r, const Operand& op) { opGpr(Reg32e(1, r.getBit()), op, r, T_0F38, 0xf3, false); }
+void bndcl(const BoundsReg& bnd, const Operand& op) { db(0xF3); opR_ModM(op, i32e, bnd.getIdx(), 0x0F, 0x1A, NONE, !op.isMEM()); }
+void bndcn(const BoundsReg& bnd, const Operand& op) { db(0xF2); opR_ModM(op, i32e, bnd.getIdx(), 0x0F, 0x1B, NONE, !op.isMEM()); }
+void bndcu(const BoundsReg& bnd, const Operand& op) { db(0xF2); opR_ModM(op, i32e, bnd.getIdx(), 0x0F, 0x1A, NONE, !op.isMEM()); }
+void bndldx(const BoundsReg& bnd, const Address& addr) { opModM(addr, bnd, 0x0F, 0x1A); }
+void bndmk(const BoundsReg& bnd, const Address& addr) { db(0xF3); opModM(addr, bnd, 0x0F, 0x1B); }
+void bndmov(const Address& addr, const BoundsReg& bnd) { db(0x66); opModM(addr, bnd, 0x0F, 0x1B); }
+void bndmov(const BoundsReg& bnd, const Operand& op) { db(0x66); opModRM(bnd, op, op.isBNDREG(), op.isMEM(), 0x0F, 0x1A); }
+void bndstx(const Address& addr, const BoundsReg& bnd) { opModM(addr, bnd, 0x0F, 0x1B); }
void bsf(const Reg®, const Operand& op) { opModRM(reg, op, op.isREG(16 | i32e), op.isMEM(), 0x0F, 0xBC); }
void bsr(const Reg®, const Operand& op) { opModRM(reg, op, op.isREG(16 | i32e), op.isMEM(), 0x0F, 0xBD); }
void bswap(const Reg32e& reg) { opModR(Reg32(1), reg, 0x0F); }
diff --git a/xbyak/xbyak_util.h b/xbyak/xbyak_util.h
index 82c8b9e..eb65004 100644
--- a/xbyak/xbyak_util.h
+++ b/xbyak/xbyak_util.h
@@ -177,6 +177,7 @@
static const Type tPREFETCHWT1 = uint64(1) << 46;
static const Type tPREFETCHW = uint64(1) << 47;
static const Type tSHA = uint64(1) << 48;
+ static const Type tMPX = uint64(1) << 49;
Cpu()
: type_(NONE)
@@ -255,6 +256,7 @@
if (data[1] & (1U << 20)) type_ |= tSMAP;
if (data[1] & (1U << 4)) type_ |= tHLE;
if (data[1] & (1U << 11)) type_ |= tRTM;
+ if (data[1] & (1U << 14)) type_ |= tMPX;
if (data[1] & (1U << 29)) type_ |= tSHA;
if (data[2] & (1U << 0)) type_ |= tPREFETCHWT1;
}
