| --- a/core/iwasm/interpreter/wasm_interp_fast.c | |
| +++ b/core/iwasm/interpreter/wasm_interp_fast.c | |
| @@ -1641,6 +1641,9 @@ | |
| #if WASM_ENABLE_LABELS_AS_VALUES != 0 | |
| static void **global_handle_table; | |
| +#if WASM_ENABLE_SIMDE != 0 | |
| +static void **global_simd_handle_table; | |
| +#endif | |
| #endif | |
| static inline uint8 * | |
| @@ -1757,8 +1760,253 @@ | |
| #define HANDLE_OPCODE(op) &&HANDLE_##op | |
| DEFINE_GOTO_TABLE(const void *, handle_table); | |
| #undef HANDLE_OPCODE | |
| +#if WASM_ENABLE_SIMDE != 0 | |
| + /* rive patch: initialized statically, as concurrent loads read it */ | |
| + static const void *simd_handle_table[256] = { | |
| + [0 ... 255] = &&HANDLE_SIMD_unsupported, | |
| + [SIMD_v128_load] = &&HANDLE_SIMD_SIMD_v128_load, | |
| + [SIMD_v128_load8x8_s] = &&HANDLE_SIMD_SIMD_v128_load8x8_s, | |
| + [SIMD_v128_load8x8_u] = &&HANDLE_SIMD_SIMD_v128_load8x8_u, | |
| + [SIMD_v128_load16x4_s] = &&HANDLE_SIMD_SIMD_v128_load16x4_s, | |
| + [SIMD_v128_load16x4_u] = &&HANDLE_SIMD_SIMD_v128_load16x4_u, | |
| + [SIMD_v128_load32x2_s] = &&HANDLE_SIMD_SIMD_v128_load32x2_s, | |
| + [SIMD_v128_load32x2_u] = &&HANDLE_SIMD_SIMD_v128_load32x2_u, | |
| + [SIMD_v128_load8_splat] = &&HANDLE_SIMD_SIMD_v128_load8_splat, | |
| + [SIMD_v128_load16_splat] = &&HANDLE_SIMD_SIMD_v128_load16_splat, | |
| + [SIMD_v128_load32_splat] = &&HANDLE_SIMD_SIMD_v128_load32_splat, | |
| + [SIMD_v128_load64_splat] = &&HANDLE_SIMD_SIMD_v128_load64_splat, | |
| + [SIMD_v128_store] = &&HANDLE_SIMD_SIMD_v128_store, | |
| + [SIMD_v128_const] = &&HANDLE_SIMD_SIMD_v128_const, | |
| + [SIMD_v8x16_shuffle] = &&HANDLE_SIMD_SIMD_v8x16_shuffle, | |
| + [SIMD_v8x16_swizzle] = &&HANDLE_SIMD_SIMD_v8x16_swizzle, | |
| + [SIMD_i8x16_splat] = &&HANDLE_SIMD_SIMD_i8x16_splat, | |
| + [SIMD_i16x8_splat] = &&HANDLE_SIMD_SIMD_i16x8_splat, | |
| + [SIMD_i32x4_splat] = &&HANDLE_SIMD_SIMD_i32x4_splat, | |
| + [SIMD_i64x2_splat] = &&HANDLE_SIMD_SIMD_i64x2_splat, | |
| + [SIMD_f32x4_splat] = &&HANDLE_SIMD_SIMD_f32x4_splat, | |
| + [SIMD_f64x2_splat] = &&HANDLE_SIMD_SIMD_f64x2_splat, | |
| + [SIMD_i8x16_extract_lane_s] = &&HANDLE_SIMD_SIMD_i8x16_extract_lane_s, | |
| + [SIMD_i8x16_extract_lane_u] = &&HANDLE_SIMD_SIMD_i8x16_extract_lane_u, | |
| + [SIMD_i8x16_replace_lane] = &&HANDLE_SIMD_SIMD_i8x16_replace_lane, | |
| + [SIMD_i16x8_extract_lane_s] = &&HANDLE_SIMD_SIMD_i16x8_extract_lane_s, | |
| + [SIMD_i16x8_extract_lane_u] = &&HANDLE_SIMD_SIMD_i16x8_extract_lane_u, | |
| + [SIMD_i16x8_replace_lane] = &&HANDLE_SIMD_SIMD_i16x8_replace_lane, | |
| + [SIMD_i32x4_extract_lane] = &&HANDLE_SIMD_SIMD_i32x4_extract_lane, | |
| + [SIMD_i32x4_replace_lane] = &&HANDLE_SIMD_SIMD_i32x4_replace_lane, | |
| + [SIMD_i64x2_extract_lane] = &&HANDLE_SIMD_SIMD_i64x2_extract_lane, | |
| + [SIMD_i64x2_replace_lane] = &&HANDLE_SIMD_SIMD_i64x2_replace_lane, | |
| + [SIMD_f32x4_extract_lane] = &&HANDLE_SIMD_SIMD_f32x4_extract_lane, | |
| + [SIMD_f32x4_replace_lane] = &&HANDLE_SIMD_SIMD_f32x4_replace_lane, | |
| + [SIMD_f64x2_extract_lane] = &&HANDLE_SIMD_SIMD_f64x2_extract_lane, | |
| + [SIMD_f64x2_replace_lane] = &&HANDLE_SIMD_SIMD_f64x2_replace_lane, | |
| + [SIMD_i8x16_eq] = &&HANDLE_SIMD_SIMD_i8x16_eq, | |
| + [SIMD_i8x16_ne] = &&HANDLE_SIMD_SIMD_i8x16_ne, | |
| + [SIMD_i8x16_lt_s] = &&HANDLE_SIMD_SIMD_i8x16_lt_s, | |
| + [SIMD_i8x16_lt_u] = &&HANDLE_SIMD_SIMD_i8x16_lt_u, | |
| + [SIMD_i8x16_gt_s] = &&HANDLE_SIMD_SIMD_i8x16_gt_s, | |
| + [SIMD_i8x16_gt_u] = &&HANDLE_SIMD_SIMD_i8x16_gt_u, | |
| + [SIMD_i8x16_le_s] = &&HANDLE_SIMD_SIMD_i8x16_le_s, | |
| + [SIMD_i8x16_le_u] = &&HANDLE_SIMD_SIMD_i8x16_le_u, | |
| + [SIMD_i8x16_ge_s] = &&HANDLE_SIMD_SIMD_i8x16_ge_s, | |
| + [SIMD_i8x16_ge_u] = &&HANDLE_SIMD_SIMD_i8x16_ge_u, | |
| + [SIMD_i16x8_eq] = &&HANDLE_SIMD_SIMD_i16x8_eq, | |
| + [SIMD_i16x8_ne] = &&HANDLE_SIMD_SIMD_i16x8_ne, | |
| + [SIMD_i16x8_lt_s] = &&HANDLE_SIMD_SIMD_i16x8_lt_s, | |
| + [SIMD_i16x8_lt_u] = &&HANDLE_SIMD_SIMD_i16x8_lt_u, | |
| + [SIMD_i16x8_gt_s] = &&HANDLE_SIMD_SIMD_i16x8_gt_s, | |
| + [SIMD_i16x8_gt_u] = &&HANDLE_SIMD_SIMD_i16x8_gt_u, | |
| + [SIMD_i16x8_le_s] = &&HANDLE_SIMD_SIMD_i16x8_le_s, | |
| + [SIMD_i16x8_le_u] = &&HANDLE_SIMD_SIMD_i16x8_le_u, | |
| + [SIMD_i16x8_ge_s] = &&HANDLE_SIMD_SIMD_i16x8_ge_s, | |
| + [SIMD_i16x8_ge_u] = &&HANDLE_SIMD_SIMD_i16x8_ge_u, | |
| + [SIMD_i32x4_eq] = &&HANDLE_SIMD_SIMD_i32x4_eq, | |
| + [SIMD_i32x4_ne] = &&HANDLE_SIMD_SIMD_i32x4_ne, | |
| + [SIMD_i32x4_lt_s] = &&HANDLE_SIMD_SIMD_i32x4_lt_s, | |
| + [SIMD_i32x4_lt_u] = &&HANDLE_SIMD_SIMD_i32x4_lt_u, | |
| + [SIMD_i32x4_gt_s] = &&HANDLE_SIMD_SIMD_i32x4_gt_s, | |
| + [SIMD_i32x4_gt_u] = &&HANDLE_SIMD_SIMD_i32x4_gt_u, | |
| + [SIMD_i32x4_le_s] = &&HANDLE_SIMD_SIMD_i32x4_le_s, | |
| + [SIMD_i32x4_le_u] = &&HANDLE_SIMD_SIMD_i32x4_le_u, | |
| + [SIMD_i32x4_ge_s] = &&HANDLE_SIMD_SIMD_i32x4_ge_s, | |
| + [SIMD_i32x4_ge_u] = &&HANDLE_SIMD_SIMD_i32x4_ge_u, | |
| + [SIMD_f32x4_eq] = &&HANDLE_SIMD_SIMD_f32x4_eq, | |
| + [SIMD_f32x4_ne] = &&HANDLE_SIMD_SIMD_f32x4_ne, | |
| + [SIMD_f32x4_lt] = &&HANDLE_SIMD_SIMD_f32x4_lt, | |
| + [SIMD_f32x4_gt] = &&HANDLE_SIMD_SIMD_f32x4_gt, | |
| + [SIMD_f32x4_le] = &&HANDLE_SIMD_SIMD_f32x4_le, | |
| + [SIMD_f32x4_ge] = &&HANDLE_SIMD_SIMD_f32x4_ge, | |
| + [SIMD_f64x2_eq] = &&HANDLE_SIMD_SIMD_f64x2_eq, | |
| + [SIMD_f64x2_ne] = &&HANDLE_SIMD_SIMD_f64x2_ne, | |
| + [SIMD_f64x2_lt] = &&HANDLE_SIMD_SIMD_f64x2_lt, | |
| + [SIMD_f64x2_gt] = &&HANDLE_SIMD_SIMD_f64x2_gt, | |
| + [SIMD_f64x2_le] = &&HANDLE_SIMD_SIMD_f64x2_le, | |
| + [SIMD_f64x2_ge] = &&HANDLE_SIMD_SIMD_f64x2_ge, | |
| + [SIMD_v128_not] = &&HANDLE_SIMD_SIMD_v128_not, | |
| + [SIMD_v128_and] = &&HANDLE_SIMD_SIMD_v128_and, | |
| + [SIMD_v128_andnot] = &&HANDLE_SIMD_SIMD_v128_andnot, | |
| + [SIMD_v128_or] = &&HANDLE_SIMD_SIMD_v128_or, | |
| + [SIMD_v128_xor] = &&HANDLE_SIMD_SIMD_v128_xor, | |
| + [SIMD_v128_bitselect] = &&HANDLE_SIMD_SIMD_v128_bitselect, | |
| + [SIMD_v128_any_true] = &&HANDLE_SIMD_SIMD_v128_any_true, | |
| + [SIMD_v128_load8_lane] = &&HANDLE_SIMD_SIMD_v128_load8_lane, | |
| + [SIMD_v128_load16_lane] = &&HANDLE_SIMD_SIMD_v128_load16_lane, | |
| + [SIMD_v128_load32_lane] = &&HANDLE_SIMD_SIMD_v128_load32_lane, | |
| + [SIMD_v128_load64_lane] = &&HANDLE_SIMD_SIMD_v128_load64_lane, | |
| + [SIMD_v128_store8_lane] = &&HANDLE_SIMD_SIMD_v128_store8_lane, | |
| + [SIMD_v128_store16_lane] = &&HANDLE_SIMD_SIMD_v128_store16_lane, | |
| + [SIMD_v128_store32_lane] = &&HANDLE_SIMD_SIMD_v128_store32_lane, | |
| + [SIMD_v128_store64_lane] = &&HANDLE_SIMD_SIMD_v128_store64_lane, | |
| + [SIMD_v128_load32_zero] = &&HANDLE_SIMD_SIMD_v128_load32_zero, | |
| + [SIMD_v128_load64_zero] = &&HANDLE_SIMD_SIMD_v128_load64_zero, | |
| + [SIMD_f32x4_demote_f64x2_zero] = &&HANDLE_SIMD_SIMD_f32x4_demote_f64x2_zero, | |
| + [SIMD_f64x2_promote_low_f32x4_zero] = &&HANDLE_SIMD_SIMD_f64x2_promote_low_f32x4_zero, | |
| + [SIMD_i8x16_abs] = &&HANDLE_SIMD_SIMD_i8x16_abs, | |
| + [SIMD_i8x16_neg] = &&HANDLE_SIMD_SIMD_i8x16_neg, | |
| + [SIMD_i8x16_popcnt] = &&HANDLE_SIMD_SIMD_i8x16_popcnt, | |
| + [SIMD_i8x16_all_true] = &&HANDLE_SIMD_SIMD_i8x16_all_true, | |
| + [SIMD_i8x16_bitmask] = &&HANDLE_SIMD_SIMD_i8x16_bitmask, | |
| + [SIMD_i8x16_narrow_i16x8_s] = &&HANDLE_SIMD_SIMD_i8x16_narrow_i16x8_s, | |
| + [SIMD_i8x16_narrow_i16x8_u] = &&HANDLE_SIMD_SIMD_i8x16_narrow_i16x8_u, | |
| + [SIMD_f32x4_ceil] = &&HANDLE_SIMD_SIMD_f32x4_ceil, | |
| + [SIMD_f32x4_floor] = &&HANDLE_SIMD_SIMD_f32x4_floor, | |
| + [SIMD_f32x4_trunc] = &&HANDLE_SIMD_SIMD_f32x4_trunc, | |
| + [SIMD_f32x4_nearest] = &&HANDLE_SIMD_SIMD_f32x4_nearest, | |
| + [SIMD_i8x16_shl] = &&HANDLE_SIMD_SIMD_i8x16_shl, | |
| + [SIMD_i8x16_shr_s] = &&HANDLE_SIMD_SIMD_i8x16_shr_s, | |
| + [SIMD_i8x16_shr_u] = &&HANDLE_SIMD_SIMD_i8x16_shr_u, | |
| + [SIMD_i8x16_add] = &&HANDLE_SIMD_SIMD_i8x16_add, | |
| + [SIMD_i8x16_add_sat_s] = &&HANDLE_SIMD_SIMD_i8x16_add_sat_s, | |
| + [SIMD_i8x16_add_sat_u] = &&HANDLE_SIMD_SIMD_i8x16_add_sat_u, | |
| + [SIMD_i8x16_sub] = &&HANDLE_SIMD_SIMD_i8x16_sub, | |
| + [SIMD_i8x16_sub_sat_s] = &&HANDLE_SIMD_SIMD_i8x16_sub_sat_s, | |
| + [SIMD_i8x16_sub_sat_u] = &&HANDLE_SIMD_SIMD_i8x16_sub_sat_u, | |
| + [SIMD_f64x2_ceil] = &&HANDLE_SIMD_SIMD_f64x2_ceil, | |
| + [SIMD_f64x2_floor] = &&HANDLE_SIMD_SIMD_f64x2_floor, | |
| + [SIMD_i8x16_min_s] = &&HANDLE_SIMD_SIMD_i8x16_min_s, | |
| + [SIMD_i8x16_min_u] = &&HANDLE_SIMD_SIMD_i8x16_min_u, | |
| + [SIMD_i8x16_max_s] = &&HANDLE_SIMD_SIMD_i8x16_max_s, | |
| + [SIMD_i8x16_max_u] = &&HANDLE_SIMD_SIMD_i8x16_max_u, | |
| + [SIMD_f64x2_trunc] = &&HANDLE_SIMD_SIMD_f64x2_trunc, | |
| + [SIMD_i8x16_avgr_u] = &&HANDLE_SIMD_SIMD_i8x16_avgr_u, | |
| + [SIMD_i16x8_extadd_pairwise_i8x16_s] = &&HANDLE_SIMD_SIMD_i16x8_extadd_pairwise_i8x16_s, | |
| + [SIMD_i16x8_extadd_pairwise_i8x16_u] = &&HANDLE_SIMD_SIMD_i16x8_extadd_pairwise_i8x16_u, | |
| + [SIMD_i32x4_extadd_pairwise_i16x8_s] = &&HANDLE_SIMD_SIMD_i32x4_extadd_pairwise_i16x8_s, | |
| + [SIMD_i32x4_extadd_pairwise_i16x8_u] = &&HANDLE_SIMD_SIMD_i32x4_extadd_pairwise_i16x8_u, | |
| + [SIMD_i16x8_abs] = &&HANDLE_SIMD_SIMD_i16x8_abs, | |
| + [SIMD_i16x8_neg] = &&HANDLE_SIMD_SIMD_i16x8_neg, | |
| + [SIMD_i16x8_q15mulr_sat_s] = &&HANDLE_SIMD_SIMD_i16x8_q15mulr_sat_s, | |
| + [SIMD_i16x8_all_true] = &&HANDLE_SIMD_SIMD_i16x8_all_true, | |
| + [SIMD_i16x8_bitmask] = &&HANDLE_SIMD_SIMD_i16x8_bitmask, | |
| + [SIMD_i16x8_narrow_i32x4_s] = &&HANDLE_SIMD_SIMD_i16x8_narrow_i32x4_s, | |
| + [SIMD_i16x8_narrow_i32x4_u] = &&HANDLE_SIMD_SIMD_i16x8_narrow_i32x4_u, | |
| + [SIMD_i16x8_extend_low_i8x16_s] = &&HANDLE_SIMD_SIMD_i16x8_extend_low_i8x16_s, | |
| + [SIMD_i16x8_extend_high_i8x16_s] = &&HANDLE_SIMD_SIMD_i16x8_extend_high_i8x16_s, | |
| + [SIMD_i16x8_extend_low_i8x16_u] = &&HANDLE_SIMD_SIMD_i16x8_extend_low_i8x16_u, | |
| + [SIMD_i16x8_extend_high_i8x16_u] = &&HANDLE_SIMD_SIMD_i16x8_extend_high_i8x16_u, | |
| + [SIMD_i16x8_shl] = &&HANDLE_SIMD_SIMD_i16x8_shl, | |
| + [SIMD_i16x8_shr_s] = &&HANDLE_SIMD_SIMD_i16x8_shr_s, | |
| + [SIMD_i16x8_shr_u] = &&HANDLE_SIMD_SIMD_i16x8_shr_u, | |
| + [SIMD_i16x8_add] = &&HANDLE_SIMD_SIMD_i16x8_add, | |
| + [SIMD_i16x8_add_sat_s] = &&HANDLE_SIMD_SIMD_i16x8_add_sat_s, | |
| + [SIMD_i16x8_add_sat_u] = &&HANDLE_SIMD_SIMD_i16x8_add_sat_u, | |
| + [SIMD_i16x8_sub] = &&HANDLE_SIMD_SIMD_i16x8_sub, | |
| + [SIMD_i16x8_sub_sat_s] = &&HANDLE_SIMD_SIMD_i16x8_sub_sat_s, | |
| + [SIMD_i16x8_sub_sat_u] = &&HANDLE_SIMD_SIMD_i16x8_sub_sat_u, | |
| + [SIMD_f64x2_nearest] = &&HANDLE_SIMD_SIMD_f64x2_nearest, | |
| + [SIMD_i16x8_mul] = &&HANDLE_SIMD_SIMD_i16x8_mul, | |
| + [SIMD_i16x8_min_s] = &&HANDLE_SIMD_SIMD_i16x8_min_s, | |
| + [SIMD_i16x8_min_u] = &&HANDLE_SIMD_SIMD_i16x8_min_u, | |
| + [SIMD_i16x8_max_s] = &&HANDLE_SIMD_SIMD_i16x8_max_s, | |
| + [SIMD_i16x8_max_u] = &&HANDLE_SIMD_SIMD_i16x8_max_u, | |
| + [SIMD_i16x8_avgr_u] = &&HANDLE_SIMD_SIMD_i16x8_avgr_u, | |
| + [SIMD_i16x8_extmul_low_i8x16_s] = &&HANDLE_SIMD_SIMD_i16x8_extmul_low_i8x16_s, | |
| + [SIMD_i16x8_extmul_high_i8x16_s] = &&HANDLE_SIMD_SIMD_i16x8_extmul_high_i8x16_s, | |
| + [SIMD_i16x8_extmul_low_i8x16_u] = &&HANDLE_SIMD_SIMD_i16x8_extmul_low_i8x16_u, | |
| + [SIMD_i16x8_extmul_high_i8x16_u] = &&HANDLE_SIMD_SIMD_i16x8_extmul_high_i8x16_u, | |
| + [SIMD_i32x4_abs] = &&HANDLE_SIMD_SIMD_i32x4_abs, | |
| + [SIMD_i32x4_neg] = &&HANDLE_SIMD_SIMD_i32x4_neg, | |
| + [SIMD_i32x4_all_true] = &&HANDLE_SIMD_SIMD_i32x4_all_true, | |
| + [SIMD_i32x4_bitmask] = &&HANDLE_SIMD_SIMD_i32x4_bitmask, | |
| + [SIMD_i32x4_extend_low_i16x8_s] = &&HANDLE_SIMD_SIMD_i32x4_extend_low_i16x8_s, | |
| + [SIMD_i32x4_extend_high_i16x8_s] = &&HANDLE_SIMD_SIMD_i32x4_extend_high_i16x8_s, | |
| + [SIMD_i32x4_extend_low_i16x8_u] = &&HANDLE_SIMD_SIMD_i32x4_extend_low_i16x8_u, | |
| + [SIMD_i32x4_extend_high_i16x8_u] = &&HANDLE_SIMD_SIMD_i32x4_extend_high_i16x8_u, | |
| + [SIMD_i32x4_shl] = &&HANDLE_SIMD_SIMD_i32x4_shl, | |
| + [SIMD_i32x4_shr_s] = &&HANDLE_SIMD_SIMD_i32x4_shr_s, | |
| + [SIMD_i32x4_shr_u] = &&HANDLE_SIMD_SIMD_i32x4_shr_u, | |
| + [SIMD_i32x4_add] = &&HANDLE_SIMD_SIMD_i32x4_add, | |
| + [SIMD_i32x4_sub] = &&HANDLE_SIMD_SIMD_i32x4_sub, | |
| + [SIMD_i32x4_mul] = &&HANDLE_SIMD_SIMD_i32x4_mul, | |
| + [SIMD_i32x4_min_s] = &&HANDLE_SIMD_SIMD_i32x4_min_s, | |
| + [SIMD_i32x4_min_u] = &&HANDLE_SIMD_SIMD_i32x4_min_u, | |
| + [SIMD_i32x4_max_s] = &&HANDLE_SIMD_SIMD_i32x4_max_s, | |
| + [SIMD_i32x4_max_u] = &&HANDLE_SIMD_SIMD_i32x4_max_u, | |
| + [SIMD_i32x4_dot_i16x8_s] = &&HANDLE_SIMD_SIMD_i32x4_dot_i16x8_s, | |
| + [SIMD_i32x4_extmul_low_i16x8_s] = &&HANDLE_SIMD_SIMD_i32x4_extmul_low_i16x8_s, | |
| + [SIMD_i32x4_extmul_high_i16x8_s] = &&HANDLE_SIMD_SIMD_i32x4_extmul_high_i16x8_s, | |
| + [SIMD_i32x4_extmul_low_i16x8_u] = &&HANDLE_SIMD_SIMD_i32x4_extmul_low_i16x8_u, | |
| + [SIMD_i32x4_extmul_high_i16x8_u] = &&HANDLE_SIMD_SIMD_i32x4_extmul_high_i16x8_u, | |
| + [SIMD_i64x2_abs] = &&HANDLE_SIMD_SIMD_i64x2_abs, | |
| + [SIMD_i64x2_neg] = &&HANDLE_SIMD_SIMD_i64x2_neg, | |
| + [SIMD_i64x2_all_true] = &&HANDLE_SIMD_SIMD_i64x2_all_true, | |
| + [SIMD_i64x2_bitmask] = &&HANDLE_SIMD_SIMD_i64x2_bitmask, | |
| + [SIMD_i64x2_extend_low_i32x4_s] = &&HANDLE_SIMD_SIMD_i64x2_extend_low_i32x4_s, | |
| + [SIMD_i64x2_extend_high_i32x4_s] = &&HANDLE_SIMD_SIMD_i64x2_extend_high_i32x4_s, | |
| + [SIMD_i64x2_extend_low_i32x4_u] = &&HANDLE_SIMD_SIMD_i64x2_extend_low_i32x4_u, | |
| + [SIMD_i64x2_extend_high_i32x4_u] = &&HANDLE_SIMD_SIMD_i64x2_extend_high_i32x4_u, | |
| + [SIMD_i64x2_shl] = &&HANDLE_SIMD_SIMD_i64x2_shl, | |
| + [SIMD_i64x2_shr_s] = &&HANDLE_SIMD_SIMD_i64x2_shr_s, | |
| + [SIMD_i64x2_shr_u] = &&HANDLE_SIMD_SIMD_i64x2_shr_u, | |
| + [SIMD_i64x2_add] = &&HANDLE_SIMD_SIMD_i64x2_add, | |
| + [SIMD_i64x2_sub] = &&HANDLE_SIMD_SIMD_i64x2_sub, | |
| + [SIMD_i64x2_mul] = &&HANDLE_SIMD_SIMD_i64x2_mul, | |
| + [SIMD_i64x2_eq] = &&HANDLE_SIMD_SIMD_i64x2_eq, | |
| + [SIMD_i64x2_ne] = &&HANDLE_SIMD_SIMD_i64x2_ne, | |
| + [SIMD_i64x2_lt_s] = &&HANDLE_SIMD_SIMD_i64x2_lt_s, | |
| + [SIMD_i64x2_gt_s] = &&HANDLE_SIMD_SIMD_i64x2_gt_s, | |
| + [SIMD_i64x2_le_s] = &&HANDLE_SIMD_SIMD_i64x2_le_s, | |
| + [SIMD_i64x2_ge_s] = &&HANDLE_SIMD_SIMD_i64x2_ge_s, | |
| + [SIMD_i64x2_extmul_low_i32x4_s] = &&HANDLE_SIMD_SIMD_i64x2_extmul_low_i32x4_s, | |
| + [SIMD_i64x2_extmul_high_i32x4_s] = &&HANDLE_SIMD_SIMD_i64x2_extmul_high_i32x4_s, | |
| + [SIMD_i64x2_extmul_low_i32x4_u] = &&HANDLE_SIMD_SIMD_i64x2_extmul_low_i32x4_u, | |
| + [SIMD_i64x2_extmul_high_i32x4_u] = &&HANDLE_SIMD_SIMD_i64x2_extmul_high_i32x4_u, | |
| + [SIMD_f32x4_abs] = &&HANDLE_SIMD_SIMD_f32x4_abs, | |
| + [SIMD_f32x4_neg] = &&HANDLE_SIMD_SIMD_f32x4_neg, | |
| + [SIMD_f32x4_sqrt] = &&HANDLE_SIMD_SIMD_f32x4_sqrt, | |
| + [SIMD_f32x4_add] = &&HANDLE_SIMD_SIMD_f32x4_add, | |
| + [SIMD_f32x4_sub] = &&HANDLE_SIMD_SIMD_f32x4_sub, | |
| + [SIMD_f32x4_mul] = &&HANDLE_SIMD_SIMD_f32x4_mul, | |
| + [SIMD_f32x4_div] = &&HANDLE_SIMD_SIMD_f32x4_div, | |
| + [SIMD_f32x4_min] = &&HANDLE_SIMD_SIMD_f32x4_min, | |
| + [SIMD_f32x4_max] = &&HANDLE_SIMD_SIMD_f32x4_max, | |
| + [SIMD_f32x4_pmin] = &&HANDLE_SIMD_SIMD_f32x4_pmin, | |
| + [SIMD_f32x4_pmax] = &&HANDLE_SIMD_SIMD_f32x4_pmax, | |
| + [SIMD_f64x2_abs] = &&HANDLE_SIMD_SIMD_f64x2_abs, | |
| + [SIMD_f64x2_neg] = &&HANDLE_SIMD_SIMD_f64x2_neg, | |
| + [SIMD_f64x2_sqrt] = &&HANDLE_SIMD_SIMD_f64x2_sqrt, | |
| + [SIMD_f64x2_add] = &&HANDLE_SIMD_SIMD_f64x2_add, | |
| + [SIMD_f64x2_sub] = &&HANDLE_SIMD_SIMD_f64x2_sub, | |
| + [SIMD_f64x2_mul] = &&HANDLE_SIMD_SIMD_f64x2_mul, | |
| + [SIMD_f64x2_div] = &&HANDLE_SIMD_SIMD_f64x2_div, | |
| + [SIMD_f64x2_min] = &&HANDLE_SIMD_SIMD_f64x2_min, | |
| + [SIMD_f64x2_max] = &&HANDLE_SIMD_SIMD_f64x2_max, | |
| + [SIMD_f64x2_pmin] = &&HANDLE_SIMD_SIMD_f64x2_pmin, | |
| + [SIMD_f64x2_pmax] = &&HANDLE_SIMD_SIMD_f64x2_pmax, | |
| + [SIMD_i32x4_trunc_sat_f32x4_s] = &&HANDLE_SIMD_SIMD_i32x4_trunc_sat_f32x4_s, | |
| + [SIMD_i32x4_trunc_sat_f32x4_u] = &&HANDLE_SIMD_SIMD_i32x4_trunc_sat_f32x4_u, | |
| + [SIMD_f32x4_convert_i32x4_s] = &&HANDLE_SIMD_SIMD_f32x4_convert_i32x4_s, | |
| + [SIMD_f32x4_convert_i32x4_u] = &&HANDLE_SIMD_SIMD_f32x4_convert_i32x4_u, | |
| + [SIMD_i32x4_trunc_sat_f64x2_s_zero] = &&HANDLE_SIMD_SIMD_i32x4_trunc_sat_f64x2_s_zero, | |
| + [SIMD_i32x4_trunc_sat_f64x2_u_zero] = &&HANDLE_SIMD_SIMD_i32x4_trunc_sat_f64x2_u_zero, | |
| + [SIMD_f64x2_convert_low_i32x4_s] = &&HANDLE_SIMD_SIMD_f64x2_convert_low_i32x4_s, | |
| + [SIMD_f64x2_convert_low_i32x4_u] = &&HANDLE_SIMD_SIMD_f64x2_convert_low_i32x4_u, | |
| + }; | |
| +#endif | |
| if (exec_env == NULL) { | |
| global_handle_table = (void **)handle_table; | |
| +#if WASM_ENABLE_SIMDE != 0 | |
| + global_simd_handle_table = (void **)simd_handle_table; | |
| +#endif | |
| return; | |
| } | |
| #endif | |
| @@ -6280,13 +6528,28 @@ | |
| memcpy(&(v), &(sv), sizeof(V128)); \ | |
| } while (0) | |
| +#if WASM_ENABLE_LABELS_AS_VALUES != 0 | |
| +/* rive patch: every simd sub op is a handler of its own with a replicated | |
| + dispatch tail, in place of one switch behind the prefix handler */ | |
| +#define HANDLE_SIMD_OP(op) HANDLE_SIMD_##op: | |
| +#define HANDLE_SIMD_OP_END() FETCH_OPCODE_AND_DISPATCH() | |
| +#else | |
| +#define HANDLE_SIMD_OP(op) case op: | |
| +#define HANDLE_SIMD_OP_END() break | |
| +#endif | |
| + | |
| HANDLE_OP(WASM_OP_SIMD_PREFIX) | |
| { | |
| GET_OPCODE(); | |
| - | |
| +#if WASM_ENABLE_LABELS_AS_VALUES != 0 | |
| + /* rive patch: the loader emits sub op labels directly, so | |
| + this prefix entry only serves a prefix plus byte stream */ | |
| + goto *simd_handle_table[opcode]; | |
| +#else | |
| switch (opcode) { | |
| +#endif | |
| /* Memory */ | |
| - case SIMD_v128_load: | |
| + HANDLE_SIMD_OP(SIMD_v128_load) | |
| { | |
| uint32 offset, addr; | |
| offset = read_uint32(frame_ip); | |
| @@ -6294,7 +6557,7 @@ | |
| addr_ret = GET_OFFSET(); | |
| CHECK_MEMORY_OVERFLOW(16); | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, LOAD_V128(maddr)); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_LOAD_OP(simde_func) \ | |
| do { \ | |
| @@ -6311,35 +6574,35 @@ | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); \ | |
| \ | |
| } while (0) | |
| - case SIMD_v128_load8x8_s: | |
| + HANDLE_SIMD_OP(SIMD_v128_load8x8_s) | |
| { | |
| SIMD_LOAD_OP(simde_wasm_i16x8_load8x8); | |
| - break; | |
| - } | |
| - case SIMD_v128_load8x8_u: | |
| + HANDLE_SIMD_OP_END(); | |
| + } | |
| + HANDLE_SIMD_OP(SIMD_v128_load8x8_u) | |
| { | |
| SIMD_LOAD_OP(simde_wasm_u16x8_load8x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load16x4_s: | |
| + HANDLE_SIMD_OP(SIMD_v128_load16x4_s) | |
| { | |
| SIMD_LOAD_OP(simde_wasm_i32x4_load16x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load16x4_u: | |
| + HANDLE_SIMD_OP(SIMD_v128_load16x4_u) | |
| { | |
| SIMD_LOAD_OP(simde_wasm_u32x4_load16x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load32x2_s: | |
| + HANDLE_SIMD_OP(SIMD_v128_load32x2_s) | |
| { | |
| SIMD_LOAD_OP(simde_wasm_i64x2_load32x2); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load32x2_u: | |
| + HANDLE_SIMD_OP(SIMD_v128_load32x2_u) | |
| { | |
| SIMD_LOAD_OP(simde_wasm_u64x2_load32x2); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_LOAD_SPLAT_OP(simde_func, width) \ | |
| do { \ | |
| @@ -6357,27 +6620,27 @@ | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); \ | |
| } while (0) | |
| - case SIMD_v128_load8_splat: | |
| + HANDLE_SIMD_OP(SIMD_v128_load8_splat) | |
| { | |
| SIMD_LOAD_SPLAT_OP(simde_wasm_v128_load8_splat, 8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load16_splat: | |
| + HANDLE_SIMD_OP(SIMD_v128_load16_splat) | |
| { | |
| SIMD_LOAD_SPLAT_OP(simde_wasm_v128_load16_splat, 16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load32_splat: | |
| + HANDLE_SIMD_OP(SIMD_v128_load32_splat) | |
| { | |
| SIMD_LOAD_SPLAT_OP(simde_wasm_v128_load32_splat, 32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load64_splat: | |
| + HANDLE_SIMD_OP(SIMD_v128_load64_splat) | |
| { | |
| SIMD_LOAD_SPLAT_OP(simde_wasm_v128_load64_splat, 64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_store: | |
| + HANDLE_SIMD_OP(SIMD_v128_store) | |
| { | |
| uint32 offset, addr; | |
| offset = read_uint32(frame_ip); | |
| @@ -6386,11 +6649,11 @@ | |
| CHECK_MEMORY_OVERFLOW(16); | |
| STORE_V128(maddr, data); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* Basic */ | |
| - case SIMD_v128_const: | |
| + HANDLE_SIMD_OP(SIMD_v128_const) | |
| { | |
| uint8 *orig_ip = frame_ip; | |
| @@ -6398,10 +6661,10 @@ | |
| addr_ret = GET_OFFSET(); | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, *(V128 *)orig_ip); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* TODO: Add a faster SIMD implementation */ | |
| - case SIMD_v8x16_shuffle: | |
| + HANDLE_SIMD_OP(SIMD_v8x16_shuffle) | |
| { | |
| V128 indices; | |
| bh_memcpy_s(&indices, sizeof(V128), frame_ip, | |
| @@ -6424,9 +6687,9 @@ | |
| } | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v8x16_swizzle: | |
| + HANDLE_SIMD_OP(SIMD_v8x16_swizzle) | |
| { | |
| V128 v2 = POP_V128(); | |
| V128 v1 = POP_V128(); | |
| @@ -6439,7 +6702,7 @@ | |
| SIMDE_V128_TO_SIMD_V128(simde_result, result); | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* Splat */ | |
| @@ -6463,7 +6726,7 @@ | |
| #define SIMD_SPLAT_OP_F64(simde_func) \ | |
| SIMD_SPLAT_OP(simde_func, POP_F64, float64) | |
| - case SIMD_i8x16_splat: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_splat) | |
| { | |
| val = POP_I32(); | |
| addr_ret = GET_OFFSET(); | |
| @@ -6474,32 +6737,32 @@ | |
| SIMDE_V128_TO_SIMD_V128(simde_result, result); | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_splat: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_splat) | |
| { | |
| SIMD_SPLAT_OP_I32(simde_wasm_i16x8_splat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_splat: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_splat) | |
| { | |
| SIMD_SPLAT_OP_I32(simde_wasm_i32x4_splat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_splat: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_splat) | |
| { | |
| SIMD_SPLAT_OP_I64(simde_wasm_i64x2_splat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_splat: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_splat) | |
| { | |
| SIMD_SPLAT_OP_F32(simde_wasm_f32x4_splat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_splat: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_splat) | |
| { | |
| SIMD_SPLAT_OP_F64(simde_wasm_f64x2_splat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #if WASM_CPU_SUPPORTS_UNALIGNED_ADDR_ACCESS != 0 | |
| #define SIMD_LANE_HANDLE_UNALIGNED_ACCESS() | |
| @@ -6524,75 +6787,75 @@ | |
| addr_ret = GET_OFFSET(); \ | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, v); \ | |
| } while (0) | |
| - case SIMD_i8x16_extract_lane_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_extract_lane_s) | |
| { | |
| SIMD_EXTRACT_LANE_OP(i8x16, int8, PUSH_I32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_extract_lane_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_extract_lane_u) | |
| { | |
| SIMD_EXTRACT_LANE_OP(i8x16, uint8, PUSH_I32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_replace_lane: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_replace_lane) | |
| { | |
| SIMD_REPLACE_LANE_OP(i8x16, int8, POP_I32); | |
| - break; | |
| - } | |
| - case SIMD_i16x8_extract_lane_s: | |
| + HANDLE_SIMD_OP_END(); | |
| + } | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extract_lane_s) | |
| { | |
| SIMD_EXTRACT_LANE_OP(i16x8, int16, PUSH_I32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extract_lane_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extract_lane_u) | |
| { | |
| SIMD_EXTRACT_LANE_OP(i16x8, uint16, PUSH_I32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_replace_lane: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_replace_lane) | |
| { | |
| SIMD_REPLACE_LANE_OP(i16x8, int16, POP_I32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extract_lane: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extract_lane) | |
| { | |
| SIMD_EXTRACT_LANE_OP(i32x4, int32, PUSH_I32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_replace_lane: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_replace_lane) | |
| { | |
| SIMD_REPLACE_LANE_OP(i32x4, int32, POP_I32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extract_lane: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extract_lane) | |
| { | |
| SIMD_EXTRACT_LANE_OP(i64x2, int64, PUSH_I64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_replace_lane: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_replace_lane) | |
| { | |
| SIMD_REPLACE_LANE_OP(i64x2, int64, POP_I64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_extract_lane: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_extract_lane) | |
| { | |
| SIMD_EXTRACT_LANE_OP(f32x4, float32, PUSH_F32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_replace_lane: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_replace_lane) | |
| { | |
| SIMD_REPLACE_LANE_OP(f32x4, float32, POP_F32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_extract_lane: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_extract_lane) | |
| { | |
| SIMD_EXTRACT_LANE_OP(f64x2, float64, PUSH_F64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_replace_lane: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_replace_lane) | |
| { | |
| SIMD_REPLACE_LANE_OP(f64x2, float64, POP_F64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_DOUBLE_OP(simde_func) \ | |
| @@ -6611,7 +6874,7 @@ | |
| } while (0) | |
| /* i8x16 comparison operations */ | |
| - case SIMD_i8x16_eq: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_eq) | |
| { | |
| V128 v2 = POP_V128(); | |
| V128 v1 = POP_V128(); | |
| @@ -6625,220 +6888,220 @@ | |
| SIMDE_V128_TO_SIMD_V128(simde_result, result); | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_ne: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_ne) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_ne); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_lt_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_lt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_lt_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_lt_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_gt_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_gt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_gt_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_gt_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_le_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_le_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_le_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_le_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_ge_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_ge_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_ge_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_ge_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* i16x8 comparison operations */ | |
| - case SIMD_i16x8_eq: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_eq) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_eq); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_ne: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_ne) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_ne); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_lt_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_lt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_lt_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_lt_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_gt_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_gt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_gt_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_gt_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_le_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_le_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_le_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_le_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_ge_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_ge_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_ge_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_ge_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* i32x4 comparison operations */ | |
| - case SIMD_i32x4_eq: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_eq) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_eq); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_ne: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_ne) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_ne); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_lt_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_lt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_lt_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_lt_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_gt_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_gt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_gt_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_gt_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_le_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_le_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_le_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_le_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_ge_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_ge_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_ge_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_ge_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* f32x4 comparison operations */ | |
| - case SIMD_f32x4_eq: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_eq) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_eq); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_ne: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_ne) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_ne); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_lt: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_lt) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_gt: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_gt) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_le: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_le) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_ge: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_ge) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* f64x2 comparison operations */ | |
| - case SIMD_f64x2_eq: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_eq) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_eq); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_ne: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_ne) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_ne); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_lt: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_lt) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_gt: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_gt) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_le: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_le) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_ge: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_ge) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* v128 bitwise operations */ | |
| @@ -6851,47 +7114,47 @@ | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); \ | |
| } while (0) | |
| - case SIMD_v128_not: | |
| + HANDLE_SIMD_OP(SIMD_v128_not) | |
| { | |
| V128 value = POP_V128(); | |
| SIMD_V128_BITWISE_OP_COMMON(~value.i64x2[0], | |
| ~value.i64x2[1]); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_and: | |
| + HANDLE_SIMD_OP(SIMD_v128_and) | |
| { | |
| V128 v2 = POP_V128(); | |
| V128 v1 = POP_V128(); | |
| SIMD_V128_BITWISE_OP_COMMON(v1.i64x2[0] & v2.i64x2[0], | |
| v1.i64x2[1] & v2.i64x2[1]); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_andnot: | |
| + HANDLE_SIMD_OP(SIMD_v128_andnot) | |
| { | |
| V128 v2 = POP_V128(); | |
| V128 v1 = POP_V128(); | |
| SIMD_V128_BITWISE_OP_COMMON( | |
| v1.i64x2[0] & (~v2.i64x2[0]), | |
| v1.i64x2[1] & (~v2.i64x2[1])); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_or: | |
| + HANDLE_SIMD_OP(SIMD_v128_or) | |
| { | |
| V128 v2 = POP_V128(); | |
| V128 v1 = POP_V128(); | |
| SIMD_V128_BITWISE_OP_COMMON(v1.i64x2[0] | v2.i64x2[0], | |
| v1.i64x2[1] | v2.i64x2[1]); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_xor: | |
| + HANDLE_SIMD_OP(SIMD_v128_xor) | |
| { | |
| V128 v2 = POP_V128(); | |
| V128 v1 = POP_V128(); | |
| SIMD_V128_BITWISE_OP_COMMON(v1.i64x2[0] ^ v2.i64x2[0], | |
| v1.i64x2[1] ^ v2.i64x2[1]); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_bitselect: | |
| + HANDLE_SIMD_OP(SIMD_v128_bitselect) | |
| { | |
| V128 v1 = POP_V128(); | |
| V128 v2 = POP_V128(); | |
| @@ -6907,15 +7170,15 @@ | |
| SIMDE_V128_TO_SIMD_V128(simde_result, result); | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_any_true: | |
| + HANDLE_SIMD_OP(SIMD_v128_any_true) | |
| { | |
| V128 value = POP_V128(); | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = | |
| value.i64x2[0] != 0 || value.i64x2[1] != 0; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_LOAD_LANE_COMMON(vec, register, lane, width) \ | |
| @@ -6942,25 +7205,25 @@ | |
| SIMD_LOAD_LANE_COMMON(vec, register, lane, width); \ | |
| } while (0) | |
| - case SIMD_v128_load8_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_load8_lane) | |
| { | |
| SIMD_LOAD_LANE_OP(i8x16, 8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load16_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_load16_lane) | |
| { | |
| SIMD_LOAD_LANE_OP(i16x8, 16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load32_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_load32_lane) | |
| { | |
| SIMD_LOAD_LANE_OP(i32x4, 32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load64_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_load64_lane) | |
| { | |
| SIMD_LOAD_LANE_OP(i64x2, 64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_STORE_LANE_OP(register, width) \ | |
| do { \ | |
| @@ -6979,28 +7242,28 @@ | |
| } \ | |
| } while (0) | |
| - case SIMD_v128_store8_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_store8_lane) | |
| { | |
| SIMD_STORE_LANE_OP(i8x16, 8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_store16_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_store16_lane) | |
| { | |
| SIMD_STORE_LANE_OP(i16x8, 16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_store32_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_store32_lane) | |
| { | |
| SIMD_STORE_LANE_OP(i32x4, 32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_store64_lane: | |
| + HANDLE_SIMD_OP(SIMD_v128_store64_lane) | |
| { | |
| SIMD_STORE_LANE_OP(i64x2, 64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_LOAD_ZERO_OP(register, width) \ | |
| do { \ | |
| @@ -7012,15 +7275,15 @@ | |
| SIMD_LOAD_LANE_COMMON(vec, register, lane, width); \ | |
| } while (0) | |
| - case SIMD_v128_load32_zero: | |
| + HANDLE_SIMD_OP(SIMD_v128_load32_zero) | |
| { | |
| SIMD_LOAD_ZERO_OP(i32x4, 32); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_v128_load64_zero: | |
| + HANDLE_SIMD_OP(SIMD_v128_load64_zero) | |
| { | |
| SIMD_LOAD_ZERO_OP(i64x2, 64); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_SINGLE_OP(simde_func) \ | |
| @@ -7037,34 +7300,34 @@ | |
| } while (0) | |
| /* Float conversion */ | |
| - case SIMD_f32x4_demote_f64x2_zero: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_demote_f64x2_zero) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_demote_f64x2_zero); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_promote_low_f32x4_zero: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_promote_low_f32x4_zero) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_promote_low_f32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* i8x16 operations */ | |
| - case SIMD_i8x16_abs: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_abs) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i8x16_abs); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_neg: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_neg) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i8x16_neg); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_popcnt: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_popcnt) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i8x16_popcnt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_all_true: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_all_true) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7073,10 +7336,10 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_bitmask: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_bitmask) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7085,37 +7348,37 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_narrow_i16x8_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_narrow_i16x8_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_narrow_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_narrow_i16x8_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_narrow_i16x8_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_narrow_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_ceil: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_ceil) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_ceil); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_floor: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_floor) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_floor); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_trunc: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_trunc) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_trunc); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_nearest: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_nearest) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_nearest); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| #define SIMD_LANE_SHIFT(simde_func) \ | |
| do { \ | |
| @@ -7131,129 +7394,129 @@ | |
| \ | |
| PUT_V128_TO_ADDR(frame_lp + addr_ret, result); \ | |
| } while (0) | |
| - case SIMD_i8x16_shl: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_shl) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i8x16_shl); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_shr_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_shr_s) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i8x16_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_shr_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_shr_u) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_u8x16_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_add: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_add) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_add); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_add_sat_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_add_sat_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_add_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_add_sat_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_add_sat_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_add_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_sub: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_sub) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_sub); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_sub_sat_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_sub_sat_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_sub_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_sub_sat_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_sub_sat_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_sub_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_ceil: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_ceil) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_ceil); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_floor: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_floor) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_floor); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_min_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_min_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_min_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_min_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_max_s: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_max_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i8x16_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_max_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_max_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_trunc: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_trunc) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_trunc); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i8x16_avgr_u: | |
| + HANDLE_SIMD_OP(SIMD_i8x16_avgr_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u8x16_avgr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extadd_pairwise_i8x16_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extadd_pairwise_i8x16_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i16x8_extadd_pairwise_i8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extadd_pairwise_i8x16_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extadd_pairwise_i8x16_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u16x8_extadd_pairwise_u8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extadd_pairwise_i16x8_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extadd_pairwise_i16x8_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i32x4_extadd_pairwise_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extadd_pairwise_i16x8_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extadd_pairwise_i16x8_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u32x4_extadd_pairwise_u16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* i16x8 operations */ | |
| - case SIMD_i16x8_abs: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_abs) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i16x8_abs); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_neg: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_neg) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i16x8_neg); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_q15mulr_sat_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_q15mulr_sat_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_q15mulr_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_all_true: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_all_true) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7262,9 +7525,9 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_bitmask: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_bitmask) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7273,151 +7536,151 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_narrow_i32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_narrow_i32x4_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_narrow_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_narrow_i32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_narrow_i32x4_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_narrow_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extend_low_i8x16_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extend_low_i8x16_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i16x8_extend_low_i8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extend_high_i8x16_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extend_high_i8x16_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i16x8_extend_high_i8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extend_low_i8x16_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extend_low_i8x16_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u16x8_extend_low_u8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extend_high_i8x16_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extend_high_i8x16_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u16x8_extend_high_u8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_shl: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_shl) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i16x8_shl); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_shr_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_shr_s) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i16x8_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_shr_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_shr_u) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_u16x8_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_add: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_add) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_add); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_add_sat_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_add_sat_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_add_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_add_sat_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_add_sat_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_add_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_sub: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_sub) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_sub); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_sub_sat_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_sub_sat_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_sub_sat); | |
| - break; | |
| - } | |
| - case SIMD_i16x8_sub_sat_u: | |
| + HANDLE_SIMD_OP_END(); | |
| + } | |
| + HANDLE_SIMD_OP(SIMD_i16x8_sub_sat_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_sub_sat); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_nearest: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_nearest) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_nearest); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_mul: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_mul) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_mul); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_min_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_min_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_min_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_min_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_max_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_max_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_max_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_max_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_avgr_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_avgr_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_avgr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extmul_low_i8x16_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extmul_low_i8x16_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_extmul_low_i8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extmul_high_i8x16_s: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extmul_high_i8x16_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i16x8_extmul_high_i8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extmul_low_i8x16_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extmul_low_i8x16_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_extmul_low_u8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i16x8_extmul_high_i8x16_u: | |
| + HANDLE_SIMD_OP(SIMD_i16x8_extmul_high_i8x16_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u16x8_extmul_high_u8x16); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* i32x4 operations */ | |
| - case SIMD_i32x4_abs: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_abs) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i32x4_abs); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_neg: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_neg) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i32x4_neg); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_all_true: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_all_true) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7426,9 +7689,9 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_bitmask: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_bitmask) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7437,116 +7700,116 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extend_low_i16x8_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extend_low_i16x8_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i32x4_extend_low_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extend_high_i16x8_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extend_high_i16x8_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i32x4_extend_high_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extend_low_i16x8_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extend_low_i16x8_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u32x4_extend_low_u16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extend_high_i16x8_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extend_high_i16x8_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u32x4_extend_high_u16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_shl: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_shl) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i32x4_shl); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_shr_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_shr_s) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i32x4_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_shr_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_shr_u) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_u32x4_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_add: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_add) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_add); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_sub: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_sub) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_sub); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_mul: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_mul) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_mul); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_min_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_min_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_min_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_min_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_max_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_max_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_max_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_max_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_dot_i16x8_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_dot_i16x8_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_dot_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extmul_low_i16x8_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extmul_low_i16x8_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_extmul_low_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extmul_high_i16x8_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extmul_high_i16x8_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i32x4_extmul_high_i16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extmul_low_i16x8_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extmul_low_i16x8_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_extmul_low_u16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_extmul_high_i16x8_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_extmul_high_i16x8_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u32x4_extmul_high_u16x8); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* i64x2 operations */ | |
| - case SIMD_i64x2_abs: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_abs) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i64x2_abs); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_neg: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_neg) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i64x2_neg); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_all_true: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_all_true) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7555,9 +7818,9 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_bitmask: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_bitmask) | |
| { | |
| V128 v1 = POP_V128(); | |
| @@ -7566,269 +7829,276 @@ | |
| addr_ret = GET_OFFSET(); | |
| frame_lp[addr_ret] = result; | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extend_low_i32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extend_low_i32x4_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i64x2_extend_low_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extend_high_i32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extend_high_i32x4_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i64x2_extend_high_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extend_low_i32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extend_low_i32x4_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u64x2_extend_low_u32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extend_high_i32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extend_high_i32x4_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u64x2_extend_high_u32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_shl: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_shl) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i64x2_shl); | |
| - break; | |
| - } | |
| - case SIMD_i64x2_shr_s: | |
| + HANDLE_SIMD_OP_END(); | |
| + } | |
| + HANDLE_SIMD_OP(SIMD_i64x2_shr_s) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_i64x2_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_shr_u: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_shr_u) | |
| { | |
| SIMD_LANE_SHIFT(simde_wasm_u64x2_shr); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_add: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_add) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_add); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_sub: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_sub) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_sub); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_mul: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_mul) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_mul); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_eq: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_eq) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_eq); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_ne: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_ne) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_ne); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_lt_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_lt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_lt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_gt_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_gt_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_gt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_le_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_le_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_le); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_ge_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_ge_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_ge); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extmul_low_i32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extmul_low_i32x4_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_extmul_low_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extmul_high_i32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extmul_high_i32x4_s) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_i64x2_extmul_high_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extmul_low_i32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extmul_low_i32x4_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u64x2_extmul_low_u32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i64x2_extmul_high_i32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_i64x2_extmul_high_i32x4_u) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_u64x2_extmul_high_u32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* f32x4 opertions */ | |
| - case SIMD_f32x4_abs: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_abs) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_abs); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_neg: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_neg) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_neg); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_sqrt: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_sqrt) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_sqrt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_add: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_add) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_add); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_sub: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_sub) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_sub); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_mul: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_mul) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_mul); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_div: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_div) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_div); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_min: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_min) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_max: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_max) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_pmin: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_pmin) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_pmin); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_pmax: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_pmax) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f32x4_pmax); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* f64x2 operations */ | |
| - case SIMD_f64x2_abs: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_abs) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_abs); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_neg: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_neg) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_neg); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_sqrt: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_sqrt) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_sqrt); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_add: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_add) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_add); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_sub: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_sub) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_sub); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_mul: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_mul) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_mul); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_div: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_div) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_div); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_min: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_min) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_min); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_max: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_max) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_max); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_pmin: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_pmin) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_pmin); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_pmax: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_pmax) | |
| { | |
| SIMD_DOUBLE_OP(simde_wasm_f64x2_pmax); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| /* Conversion operations */ | |
| - case SIMD_i32x4_trunc_sat_f32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_trunc_sat_f32x4_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i32x4_trunc_sat_f32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_trunc_sat_f32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_trunc_sat_f32x4_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u32x4_trunc_sat_f32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_convert_i32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_convert_i32x4_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_convert_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f32x4_convert_i32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_f32x4_convert_i32x4_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f32x4_convert_u32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_trunc_sat_f64x2_s_zero: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_trunc_sat_f64x2_s_zero) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_i32x4_trunc_sat_f64x2_zero); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_i32x4_trunc_sat_f64x2_u_zero: | |
| + HANDLE_SIMD_OP(SIMD_i32x4_trunc_sat_f64x2_u_zero) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_u32x4_trunc_sat_f64x2_zero); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_convert_low_i32x4_s: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_convert_low_i32x4_s) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_convert_low_i32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| - case SIMD_f64x2_convert_low_i32x4_u: | |
| + HANDLE_SIMD_OP(SIMD_f64x2_convert_low_i32x4_u) | |
| { | |
| SIMD_SINGLE_OP(simde_wasm_f64x2_convert_low_u32x4); | |
| - break; | |
| + HANDLE_SIMD_OP_END(); | |
| } | |
| +#if WASM_ENABLE_LABELS_AS_VALUES != 0 | |
| + HANDLE_SIMD_unsupported: | |
| +#else | |
| default: | |
| +#endif | |
| wasm_set_exception(module, "unsupported SIMD opcode"); | |
| + goto got_exception; | |
| +#if WASM_ENABLE_LABELS_AS_VALUES == 0 | |
| } | |
| HANDLE_OP_END(); | |
| +#endif | |
| } | |
| #endif | |
| @@ -8247,8 +8517,17 @@ | |
| memset(&module, 0, sizeof(WASMModuleInstance)); | |
| wasm_interp_call_func_bytecode(&module, NULL, NULL, NULL); | |
| return global_handle_table; | |
| +} | |
| + | |
| +#if WASM_ENABLE_SIMDE != 0 | |
| +void ** | |
| +wasm_interp_get_simd_handle_table(void) | |
| +{ | |
| + wasm_interp_get_handle_table(); | |
| + return global_simd_handle_table; | |
| } | |
| #endif | |
| +#endif | |
| #if WASM_ENABLE_GC != 0 | |
| bool | |
| --- a/core/iwasm/interpreter/wasm_loader.c | |
| +++ b/core/iwasm/interpreter/wasm_loader.c | |
| @@ -6116,7 +6116,13 @@ | |
| wasm_interp_get_handle_table(void); | |
| static void **handle_table; | |
| +#if WASM_ENABLE_SIMDE != 0 | |
| +void ** | |
| +wasm_interp_get_simd_handle_table(void); | |
| + | |
| +static void **simd_handle_table; | |
| #endif | |
| +#endif | |
| static bool | |
| load_from_sections(WASMModule *module, WASMSection *sections, | |
| @@ -6492,7 +6498,10 @@ | |
| #if WASM_ENABLE_FAST_INTERP != 0 && WASM_ENABLE_LABELS_AS_VALUES != 0 | |
| handle_table = wasm_interp_get_handle_table(); | |
| +#if WASM_ENABLE_SIMDE != 0 | |
| + simd_handle_table = wasm_interp_get_simd_handle_table(); | |
| #endif | |
| +#endif | |
| for (i = 0; i < module->function_count; i++) { | |
| WASMFunction *func = module->functions[i]; | |
| @@ -9197,6 +9206,11 @@ | |
| wasm_loader_emit_ptr(loader_ctx, handle_table[opcode]); \ | |
| LOG_OP("\nemit_op [%02x]\t", opcode); \ | |
| } while (0) | |
| +#define emit_simd_label(opcode) \ | |
| + do { \ | |
| + wasm_loader_emit_ptr(loader_ctx, simd_handle_table[opcode]); \ | |
| + LOG_OP("\nemit_simd_op [%02x]\t", opcode); \ | |
| + } while (0) | |
| #define skip_label() \ | |
| do { \ | |
| wasm_loader_emit_backspace(loader_ctx, sizeof(void *)); \ | |
| @@ -9212,6 +9226,13 @@ | |
| wasm_loader_emit_uint32(loader_ctx, offset); \ | |
| LOG_OP("\nemit_op [%02x]\t", opcode); \ | |
| } while (0) | |
| +#define emit_simd_label(opcode) \ | |
| + do { \ | |
| + int32 offset = (int32)((uint8 *)simd_handle_table[opcode] \ | |
| + - (uint8 *)handle_table[0]); \ | |
| + wasm_loader_emit_uint32(loader_ctx, offset); \ | |
| + LOG_OP("\nemit_simd_op [%02x]\t", opcode); \ | |
| + } while (0) | |
| #else | |
| #define emit_label(opcode) \ | |
| do { \ | |
| @@ -9220,6 +9241,12 @@ | |
| wasm_loader_emit_uint32(loader_ctx, label_addr); \ | |
| LOG_OP("\nemit_op [%02x]\t", opcode); \ | |
| } while (0) | |
| +#define emit_simd_label(opcode) \ | |
| + do { \ | |
| + uint32 label_addr = (uint32)(uintptr_t)simd_handle_table[opcode]; \ | |
| + wasm_loader_emit_uint32(loader_ctx, label_addr); \ | |
| + LOG_OP("\nemit_simd_op [%02x]\t", opcode); \ | |
| + } while (0) | |
| #endif | |
| #define skip_label() \ | |
| do { \ | |
| @@ -16335,8 +16362,20 @@ | |
| pb_read_leb_uint32(p, p_end, opcode1); | |
| #if WASM_ENABLE_FAST_INTERP != 0 | |
| +#if WASM_ENABLE_LABELS_AS_VALUES != 0 && WASM_ENABLE_SIMDE != 0 | |
| + /* rive patch: the sub op's own label replaces the prefix | |
| + label plus a byte, one dispatch per simd op */ | |
| + if (opcode1 <= UINT8_MAX) { | |
| + skip_label(); | |
| + emit_simd_label(opcode1); | |
| + } | |
| + else { | |
| + emit_byte(loader_ctx, opcode1); | |
| + } | |
| +#else | |
| emit_byte(loader_ctx, opcode1); | |
| #endif | |
| +#endif | |
| /* follow the order of enum WASMSimdEXTOpcode in wasm_opcode.h | |
| */ |