Add wuffs_base__cpu_arch__have_x86_sse42 for MSC
diff --git a/internal/cgen/base/fundamental-public.h b/internal/cgen/base/fundamental-public.h
index 20939d8..093d619 100644
--- a/internal/cgen/base/fundamental-public.h
+++ b/internal/cgen/base/fundamental-public.h
@@ -73,7 +73,14 @@
#define WUFFS_BASE__CPU_ARCH__X86_64
#endif // defined(__x86_64__)
-#endif // defined(__GNUC__)
+#elif defined(_MSC_VER) // defined(__GNUC__)
+
+#if defined(_M_X64)
+#include <intrin.h>
+#define WUFFS_BASE__CPU_ARCH__X86_64
+#endif // defined(__x86_64__)
+
+#endif // defined(__GNUC__); defined(_MSC_VER)
#endif // defined(WUFFS_CONFIG__AVOID_CPU_ARCH)
// --------
@@ -111,14 +118,26 @@
static inline bool //
wuffs_base__cpu_arch__have_x86_sse42() {
#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
+ // GCC defines these macros but MSVC does not.
+ // - bit_PCLMUL = (1 << 1)
+ // - bit_POPCNT = (1 << 23)
+ // - bit_SSE4_2 = (1 << 20)
+ const unsigned int sse42_ecx1 = 0x00900002;
+#if defined(__GNUC__)
unsigned int eax1 = 0;
unsigned int ebx1 = 0;
unsigned int ecx1 = 0;
unsigned int edx1 = 0;
if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {
- const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;
return (ecx1 & sse42_ecx1) == sse42_ecx1;
}
+#elif defined(_MSC_VER) // defined(__GNUC__)
+ int x[4];
+ __cpuid(x, 1);
+ return (((unsigned int)(x[2])) & sse42_ecx1) == sse42_ecx1;
+#else
+#error "WUFFS_BASE__CPU_ARCH__ETC combined with an unsupported compiler"
+#endif // defined(__GNUC__); defined(_MSC_VER)
#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
return false;
}
diff --git a/internal/cgen/data/data.go b/internal/cgen/data/data.go
index f37ee66..47b4cb6 100644
--- a/internal/cgen/data/data.go
+++ b/internal/cgen/data/data.go
@@ -55,11 +55,12 @@
"fine WUFFS_VERSION_PRE_RELEASE_LABEL \"work.in.progress\"\n#define WUFFS_VERSION_BUILD_METADATA_COMMIT_COUNT 0\n#define WUFFS_VERSION_BUILD_METADATA_COMMIT_DATE 0\n#define WUFFS_VERSION_STRING \"0.0.0+0.00000000\"\n\n" +
"" +
"// ---------------- Configuration\n\n// Define WUFFS_CONFIG__AVOID_CPU_ARCH to avoid any code tied to a specific CPU\n// architecture, such as SSE SIMD for the x86 CPU family.\n#if defined(WUFFS_CONFIG__AVOID_CPU_ARCH)\n// No-op.\n#else\n#if defined(__GNUC__)\n\n// To simplify Wuffs code, \"cpu_arch >= arm_xxx\" requires xxx but also\n// unaligned little-endian load/stores.\n#if defined(__ARM_FEATURE_UNALIGNED) && defined(__BYTE_ORDER__) && \\\n (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)\n// Not all gcc versions define __ARM_ACLE, even if they support crc32\n// intrinsics. Look for __ARM_FEATURE_CRC32 instead.\n#if defined(__ARM_FEATURE_CRC32)\n#include <arm_acle.h>\n#define WUFFS_BASE__CPU_ARCH__ARM_CRC32\n#endif // defined(__ARM_FEATURE_CRC32)\n#if defined(__ARM_NEON)\n#include <arm_neon.h>\n#define WUFFS_BASE__CPU_ARCH__ARM_NEON\n#endif // defined(__ARM_NEON)\n#endif // defined(__ARM_FEATURE_UNALIGNED) etc\n\n// Similarly, \"cpu_arch >= x86_sse42\" requires SSE4.2 but also PCLMUL and\n// POPCNT. This is checked at runtime via cpu" +
- "id, not at compile time.\n#if defined(__x86_64__)\n#include <cpuid.h>\n#include <x86intrin.h>\n#define WUFFS_BASE__CPU_ARCH__X86_64\n#endif // defined(__x86_64__)\n\n#endif // defined(__GNUC__)\n#endif // defined(WUFFS_CONFIG__AVOID_CPU_ARCH)\n\n" +
+ "id, not at compile time.\n#if defined(__x86_64__)\n#include <cpuid.h>\n#include <x86intrin.h>\n#define WUFFS_BASE__CPU_ARCH__X86_64\n#endif // defined(__x86_64__)\n\n#elif defined(_MSC_VER) // defined(__GNUC__)\n\n#if defined(_M_X64)\n#include <intrin.h>\n#define WUFFS_BASE__CPU_ARCH__X86_64\n#endif // defined(__x86_64__)\n\n#endif // defined(__GNUC__); defined(_MSC_VER)\n#endif // defined(WUFFS_CONFIG__AVOID_CPU_ARCH)\n\n" +
"" +
"// --------\n\n// Define WUFFS_CONFIG__STATIC_FUNCTIONS to make all of Wuffs' functions have\n// static storage. The motivation is discussed in the \"ALLOW STATIC\n// IMPLEMENTATION\" section of\n// https://raw.githubusercontent.com/nothings/stb/master/docs/stb_howto.txt\n#if defined(WUFFS_CONFIG__STATIC_FUNCTIONS)\n#define WUFFS_BASE__MAYBE_STATIC static\n#else\n#define WUFFS_BASE__MAYBE_STATIC\n#endif // defined(WUFFS_CONFIG__STATIC_FUNCTIONS)\n\n" +
"" +
- "// ---------------- CPU Architecture\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_arm_crc32() {\n#if defined(WUFFS_BASE__CPU_ARCH__ARM_CRC32)\n return true;\n#else\n return false;\n#endif // defined(WUFFS_BASE__CPU_ARCH__ARM_CRC32)\n}\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_arm_neon() {\n#if defined(WUFFS_BASE__CPU_ARCH__ARM_NEON)\n return true;\n#else\n return false;\n#endif // defined(WUFFS_BASE__CPU_ARCH__ARM_NEON)\n}\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_x86_sse42() {\n#if defined(WUFFS_BASE__CPU_ARCH__X86_64)\n unsigned int eax1 = 0;\n unsigned int ebx1 = 0;\n unsigned int ecx1 = 0;\n unsigned int edx1 = 0;\n if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {\n const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;\n return (ecx1 & sse42_ecx1) == sse42_ecx1;\n }\n#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)\n return false;\n}\n\n" +
+ "// ---------------- CPU Architecture\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_arm_crc32() {\n#if defined(WUFFS_BASE__CPU_ARCH__ARM_CRC32)\n return true;\n#else\n return false;\n#endif // defined(WUFFS_BASE__CPU_ARCH__ARM_CRC32)\n}\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_arm_neon() {\n#if defined(WUFFS_BASE__CPU_ARCH__ARM_NEON)\n return true;\n#else\n return false;\n#endif // defined(WUFFS_BASE__CPU_ARCH__ARM_NEON)\n}\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_x86_sse42() {\n#if defined(WUFFS_BASE__CPU_ARCH__X86_64)\n // GCC defines these macros but MSVC does not.\n // - bit_PCLMUL = (1 << 1)\n // - bit_POPCNT = (1 << 23)\n // - bit_SSE4_2 = (1 << 20)\n const unsigned int sse42_ecx1 = 0x00900002;\n#if defined(__GNUC__)\n unsigned int eax1 = 0;\n unsigned int ebx1 = 0;\n unsigned int ecx1 = 0;\n unsigned int edx1 = 0;\n if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {\n return (ecx1 & sse42_ecx1) == sse42_ecx1;\n }\n#elif defined(_MSC_VER) // defined(__GNUC__)\n int x[4];\n __cpuid(x" +
+ ", 1);\n return (((unsigned int)(x[2])) & sse42_ecx1) == sse42_ecx1;\n#else\n#error \"WUFFS_BASE__CPU_ARCH__ETC combined with an unsupported compiler\"\n#endif // defined(__GNUC__); defined(_MSC_VER)\n#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)\n return false;\n}\n\n" +
"" +
"// ---------------- Fundamentals\n\n// Wuffs assumes that:\n// - converting a uint32_t to a size_t will never overflow.\n// - converting a size_t to a uint64_t will never overflow.\n#ifdef __WORDSIZE\n#if (__WORDSIZE != 32) && (__WORDSIZE != 64)\n#error \"Wuffs requires a word size of either 32 or 64 bits\"\n#endif\n#endif\n\n#if defined(__clang__)\n#define WUFFS_BASE__POTENTIALLY_UNUSED_FIELD __attribute__((unused))\n#else\n#define WUFFS_BASE__POTENTIALLY_UNUSED_FIELD\n#endif\n\n// Clang also defines \"__GNUC__\".\n#if defined(__GNUC__)\n#define WUFFS_BASE__POTENTIALLY_UNUSED __attribute__((unused))\n#define WUFFS_BASE__WARN_UNUSED_RESULT __attribute__((warn_unused_result))\n#else\n#define WUFFS_BASE__POTENTIALLY_UNUSED\n#define WUFFS_BASE__WARN_UNUSED_RESULT\n#endif\n\n" +
"" +
diff --git a/release/c/wuffs-unsupported-snapshot.c b/release/c/wuffs-unsupported-snapshot.c
index d3358dd..c6b49c2 100644
--- a/release/c/wuffs-unsupported-snapshot.c
+++ b/release/c/wuffs-unsupported-snapshot.c
@@ -107,7 +107,14 @@
#define WUFFS_BASE__CPU_ARCH__X86_64
#endif // defined(__x86_64__)
-#endif // defined(__GNUC__)
+#elif defined(_MSC_VER) // defined(__GNUC__)
+
+#if defined(_M_X64)
+#include <intrin.h>
+#define WUFFS_BASE__CPU_ARCH__X86_64
+#endif // defined(__x86_64__)
+
+#endif // defined(__GNUC__); defined(_MSC_VER)
#endif // defined(WUFFS_CONFIG__AVOID_CPU_ARCH)
// --------
@@ -145,14 +152,26 @@
static inline bool //
wuffs_base__cpu_arch__have_x86_sse42() {
#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
+ // GCC defines these macros but MSVC does not.
+ // - bit_PCLMUL = (1 << 1)
+ // - bit_POPCNT = (1 << 23)
+ // - bit_SSE4_2 = (1 << 20)
+ const unsigned int sse42_ecx1 = 0x00900002;
+#if defined(__GNUC__)
unsigned int eax1 = 0;
unsigned int ebx1 = 0;
unsigned int ecx1 = 0;
unsigned int edx1 = 0;
if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {
- const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;
return (ecx1 & sse42_ecx1) == sse42_ecx1;
}
+#elif defined(_MSC_VER) // defined(__GNUC__)
+ int x[4];
+ __cpuid(x, 1);
+ return (((unsigned int)(x[2])) & sse42_ecx1) == sse42_ecx1;
+#else
+#error "WUFFS_BASE__CPU_ARCH__ETC combined with an unsupported compiler"
+#endif // defined(__GNUC__); defined(_MSC_VER)
#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
return false;
}
