Merge pull request #320 from CodeLinaro/spv-qcom-image-processing
SPV_QCOM_image_processing, fixes #307
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
index 7daefe6..f8a5bb2 100644
--- a/include/spirv/unified1/spirv.bf
+++ b/include/spirv/unified1/spirv.bf
@@ -578,6 +578,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1152,8 +1154,10 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
@@ -1962,6 +1966,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index 2eb5eae..c740663 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -9104,6 +9104,30 @@
"version" : "None"
},
{
+ "opname" : "OpConvertFToBF16INTEL",
+ "class" : "Conversion",
+ "opcode" : 6116,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'Float Value'" }
+ ],
+ "capabilities" : [ "BFloat16ConversionINTEL" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpConvertBF16ToFINTEL",
+ "class" : "Conversion",
+ "opcode" : 6117,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdRef", "name" : "'BFloat16 Value'" }
+ ],
+ "capabilities" : [ "BFloat16ConversionINTEL" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpControlBarrierArriveINTEL",
"class" : "Barrier",
"opcode" : 6142,
@@ -12599,6 +12623,26 @@
"version" : "None"
},
{
+ "enumerant" : "LatencyControlLabelINTEL",
+ "value" : 6172,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Latency Label'" }
+ ],
+ "capabilities" : [ "FPGALatencyControlINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "LatencyControlConstraintINTEL",
+ "value" : 6173,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Relative To'" },
+ { "kind" : "LiteralInteger", "name" : "'Control Type'" },
+ { "kind" : "LiteralInteger", "name" : "'Relative Cycle'" }
+ ],
+ "capabilities" : [ "FPGALatencyControlINTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "ConduitKernelArgumentINTEL",
"value" : 6175,
"capabilities" : [ "FPGAArgumentInterfacesINTEL" ],
@@ -14987,6 +15031,12 @@
"version" : "None"
},
{
+ "enumerant" : "BFloat16ConversionINTEL",
+ "value" : 6115,
+ "extensions" : [ "SPV_INTEL_bfloat16_conversion" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "SplitBarrierINTEL",
"value" : 6141,
"extensions" : [ "SPV_INTEL_split_barrier" ],
@@ -15000,6 +15050,12 @@
"version" : "None"
},
{
+ "enumerant" : "FPGALatencyControlINTEL",
+ "value" : 6171,
+ "extensions" : [ "SPV_INTEL_fpga_latency_control" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPGAArgumentInterfacesINTEL",
"value" : 6174,
"extensions" : [ "SPV_INTEL_fpga_argument_interfaces" ],
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index c86a14f..cb6c4f1 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -577,6 +577,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1151,8 +1153,10 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
@@ -1961,6 +1965,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index e9a584c..28eb8ff 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -583,6 +583,8 @@
SpvDecorationSingleElementVectorINTEL = 6085,
SpvDecorationVectorComputeCallableFunctionINTEL = 6087,
SpvDecorationMediaBlockIOINTEL = 6140,
+ SpvDecorationLatencyControlLabelINTEL = 6172,
+ SpvDecorationLatencyControlConstraintINTEL = 6173,
SpvDecorationConduitKernelArgumentINTEL = 6175,
SpvDecorationRegisterMapKernelArgumentINTEL = 6176,
SpvDecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1151,8 +1153,10 @@
SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
+ SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
+ SpvCapabilityFPGALatencyControlINTEL = 6171,
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMax = 0x7fffffff,
@@ -1959,6 +1963,8 @@
SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
+ SpvOpConvertFToBF16INTEL = 6116,
+ SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpGroupIMulKHR = 6401,
@@ -2666,6 +2672,8 @@
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index ef46ca9..6fd7956 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -579,6 +579,8 @@
DecorationSingleElementVectorINTEL = 6085,
DecorationVectorComputeCallableFunctionINTEL = 6087,
DecorationMediaBlockIOINTEL = 6140,
+ DecorationLatencyControlLabelINTEL = 6172,
+ DecorationLatencyControlConstraintINTEL = 6173,
DecorationConduitKernelArgumentINTEL = 6175,
DecorationRegisterMapKernelArgumentINTEL = 6176,
DecorationMMHostInterfaceAddressWidthINTEL = 6177,
@@ -1147,8 +1149,10 @@
CapabilityOptNoneINTEL = 6094,
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
+ CapabilityBFloat16ConversionINTEL = 6115,
CapabilitySplitBarrierINTEL = 6141,
CapabilityFPGAKernelAttributesv2INTEL = 6161,
+ CapabilityFPGALatencyControlINTEL = 6171,
CapabilityFPGAArgumentInterfacesINTEL = 6174,
CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMax = 0x7fffffff,
@@ -1955,6 +1959,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
@@ -2662,6 +2668,8 @@
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index 88cd6dc..362e8fa 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -579,6 +579,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1147,8 +1149,10 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Max = 0x7fffffff,
@@ -1955,6 +1959,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
@@ -2662,6 +2668,8 @@
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break;
+ case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index 6fea383..5cad41c 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -605,6 +605,8 @@
"SingleElementVectorINTEL": 6085,
"VectorComputeCallableFunctionINTEL": 6087,
"MediaBlockIOINTEL": 6140,
+ "LatencyControlLabelINTEL": 6172,
+ "LatencyControlConstraintINTEL": 6173,
"ConduitKernelArgumentINTEL": 6175,
"RegisterMapKernelArgumentINTEL": 6176,
"MMHostInterfaceAddressWidthINTEL": 6177,
@@ -1127,8 +1129,10 @@
"OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114,
+ "BFloat16ConversionINTEL": 6115,
"SplitBarrierINTEL": 6141,
"FPGAKernelAttributesv2INTEL": 6161,
+ "FPGALatencyControlINTEL": 6171,
"FPGAArgumentInterfacesINTEL": 6174,
"GroupUniformArithmeticKHR": 6400
}
@@ -1945,6 +1949,8 @@
"OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091,
"OpSpecConstantCompositeContinuedINTEL": 6092,
+ "OpConvertFToBF16INTEL": 6116,
+ "OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143,
"OpGroupIMulKHR": 6401,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index 94a0de7..88b6547 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -552,6 +552,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1109,8 +1111,10 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
},
@@ -1906,6 +1910,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index 79f3d8a..884f31a 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -552,6 +552,8 @@
'SingleElementVectorINTEL' : 6085,
'VectorComputeCallableFunctionINTEL' : 6087,
'MediaBlockIOINTEL' : 6140,
+ 'LatencyControlLabelINTEL' : 6172,
+ 'LatencyControlConstraintINTEL' : 6173,
'ConduitKernelArgumentINTEL' : 6175,
'RegisterMapKernelArgumentINTEL' : 6176,
'MMHostInterfaceAddressWidthINTEL' : 6177,
@@ -1109,8 +1111,10 @@
'OptNoneINTEL' : 6094,
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
+ 'BFloat16ConversionINTEL' : 6115,
'SplitBarrierINTEL' : 6141,
'FPGAKernelAttributesv2INTEL' : 6161,
+ 'FPGALatencyControlINTEL' : 6171,
'FPGAArgumentInterfacesINTEL' : 6174,
'GroupUniformArithmeticKHR' : 6400,
},
@@ -1906,6 +1910,8 @@
'OpTypeStructContinuedINTEL' : 6090,
'OpConstantCompositeContinuedINTEL' : 6091,
'OpSpecConstantCompositeContinuedINTEL' : 6092,
+ 'OpConvertFToBF16INTEL' : 6116,
+ 'OpConvertBF16ToFINTEL' : 6117,
'OpControlBarrierArriveINTEL' : 6142,
'OpControlBarrierWaitINTEL' : 6143,
'OpGroupIMulKHR' : 6401,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index dbb284e..315b7c8 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -580,6 +580,8 @@
SingleElementVectorINTEL = 6085,
VectorComputeCallableFunctionINTEL = 6087,
MediaBlockIOINTEL = 6140,
+ LatencyControlLabelINTEL = 6172,
+ LatencyControlConstraintINTEL = 6173,
ConduitKernelArgumentINTEL = 6175,
RegisterMapKernelArgumentINTEL = 6176,
MMHostInterfaceAddressWidthINTEL = 6177,
@@ -1154,8 +1156,10 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
+ FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
}
@@ -1964,6 +1968,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpConvertFToBF16INTEL = 6116,
+ OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
