Merge pull request #298 from MrSidims/update_intel_extensions
Update and add several Intel extensions
diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
index 4bdb937..0d6741a 100644
--- a/include/spirv/unified1/spirv.bf
+++ b/include/spirv/unified1/spirv.bf
@@ -451,6 +451,7 @@
NoCapture = 5,
NoWrite = 6,
NoReadWrite = 7,
+ RuntimeAlignedINTEL = 5940,
}
[AllowDuplicates, CRepr] public enum Decoration
@@ -559,8 +560,12 @@
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ MathOpDSPModeINTEL = 5909,
AliasScopeINTEL = 5914,
NoAliasINTEL = 5915,
+ InitiationIntervalINTEL = 5917,
+ MaxConcurrencyINTEL = 5918,
+ PipelineEnableINTEL = 5919,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -736,6 +741,8 @@
MaxInterleavingINTEL = 21,
SpeculatedIterationsINTEL = 22,
NoFusionINTEL = 23,
+ LoopCountINTEL = 24,
+ MaxReinvocationDelayINTEL = 25,
}
[AllowDuplicates, CRepr] public enum LoopControlMask
@@ -758,6 +765,8 @@
MaxInterleavingINTEL = 0x00200000,
SpeculatedIterationsINTEL = 0x00400000,
NoFusionINTEL = 0x00800000,
+ LoopCountINTEL = 0x01000000,
+ MaxReinvocationDelayINTEL = 0x02000000,
}
[AllowDuplicates, CRepr] public enum FunctionControlShift
@@ -1097,10 +1106,13 @@
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ FPGADSPControlINTEL = 5908,
MemoryAccessAliasingINTEL = 5910,
+ FPGAInvocationPipeliningAttributesINTEL = 5916,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
+ RuntimeAlignedAttributeINTEL = 5939,
IOPipesINTEL = 5943,
BlockingPipesINTEL = 5945,
FPGARegINTEL = 5948,
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index c6517c4..b20d935 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -9020,7 +9020,6 @@
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
"version" : "None"
},
{
@@ -9030,7 +9029,6 @@
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
"version" : "None"
},
{
@@ -9040,7 +9038,6 @@
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
"version" : "None"
},
{
@@ -9050,7 +9047,6 @@
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
"version" : "None"
},
{
@@ -9060,7 +9056,6 @@
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
"version" : "None"
},
{
@@ -9070,7 +9065,6 @@
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
"version" : "None"
},
{
@@ -9080,17 +9074,30 @@
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
"version" : "None"
},
{
"enumerant" : "NoFusionINTEL",
"value" : "0x800000",
+ "capabilities" : [ "FPGALoopControlsINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "LoopCountINTEL",
+ "value" : "0x1000000",
"parameters" : [
{ "kind" : "LiteralInteger" }
],
"capabilities" : [ "FPGALoopControlsINTEL" ],
- "extensions" : [ "SPV_INTEL_fpga_loop_controls" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MaxReinvocationDelayINTEL",
+ "value" : "0x2000000",
+ "parameters" : [
+ { "kind" : "LiteralInteger" }
+ ],
+ "capabilities" : [ "FPGALoopControlsINTEL" ],
"version" : "None"
}
]
@@ -11184,6 +11191,11 @@
"enumerant" : "NoReadWrite",
"value" : 7,
"capabilities" : [ "Kernel" ]
+ },
+ {
+ "enumerant" : "RuntimeAlignedINTEL",
+ "value" : 5940,
+ "capabilities" : [ "RuntimeAlignedAttributeINTEL" ]
}
]
},
@@ -11930,6 +11942,16 @@
"version" : "None"
},
{
+ "enumerant" : "MathOpDSPModeINTEL",
+ "value" : 5909,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Mode'" },
+ { "kind" : "LiteralInteger", "name" : "'Propagate'" }
+ ],
+ "capabilities" : [ "FPGADSPControlINTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "AliasScopeINTEL",
"value" : 5914,
"parameters" : [
@@ -11948,6 +11970,33 @@
"version" : "None"
},
{
+ "enumerant" : "InitiationIntervalINTEL",
+ "value" : 5917,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Cycles'" }
+ ],
+ "capabilities" : [ "FPGAInvocationPipeliningAttributesINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "MaxConcurrencyINTEL",
+ "value" : 5918,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Invocations'" }
+ ],
+ "capabilities" : [ "FPGAInvocationPipeliningAttributesINTEL" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "PipelineEnableINTEL",
+ "value" : 5919,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Enable'" }
+ ],
+ "capabilities" : [ "FPGAInvocationPipeliningAttributesINTEL" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "BufferLocationINTEL",
"value" : 5921,
"parameters" : [
@@ -14125,12 +14174,24 @@
"version" : "None"
},
{
+ "enumerant" : "FPGADSPControlINTEL",
+ "value" : 5908,
+ "extensions" : [ "SPV_INTEL_fpga_dsp_control" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "MemoryAccessAliasingINTEL",
"value" : 5910,
"extensions" : [ "SPV_INTEL_memory_access_aliasing" ],
"version" : "None"
},
{
+ "enumerant" : "FPGAInvocationPipeliningAttributesINTEL",
+ "value" : 5916,
+ "extensions" : [ "SPV_INTEL_fpga_invocation_pipelining_attributes" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "FPGABufferLocationINTEL",
"value" : 5920,
"extensions" : [ "SPV_INTEL_fpga_buffer_location" ],
@@ -14149,6 +14210,12 @@
"version" : "None"
},
{
+ "enumerant" : "RuntimeAlignedAttributeINTEL",
+ "value" : 5939,
+ "extensions" : [ "SPV_INTEL_runtime_aligned" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "IOPipesINTEL",
"value" : 5943,
"extensions" : [ "SPV_INTEL_io_pipes" ],
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 0cf3d34..192bc61 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -450,6 +450,7 @@
NoCapture = 5,
NoWrite = 6,
NoReadWrite = 7,
+ RuntimeAlignedINTEL = 5940,
}
public enum Decoration
@@ -558,8 +559,12 @@
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ MathOpDSPModeINTEL = 5909,
AliasScopeINTEL = 5914,
NoAliasINTEL = 5915,
+ InitiationIntervalINTEL = 5917,
+ MaxConcurrencyINTEL = 5918,
+ PipelineEnableINTEL = 5919,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -735,6 +740,8 @@
MaxInterleavingINTEL = 21,
SpeculatedIterationsINTEL = 22,
NoFusionINTEL = 23,
+ LoopCountINTEL = 24,
+ MaxReinvocationDelayINTEL = 25,
}
public enum LoopControlMask
@@ -757,6 +764,8 @@
MaxInterleavingINTEL = 0x00200000,
SpeculatedIterationsINTEL = 0x00400000,
NoFusionINTEL = 0x00800000,
+ LoopCountINTEL = 0x01000000,
+ MaxReinvocationDelayINTEL = 0x02000000,
}
public enum FunctionControlShift
@@ -1096,10 +1105,13 @@
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ FPGADSPControlINTEL = 5908,
MemoryAccessAliasingINTEL = 5910,
+ FPGAInvocationPipeliningAttributesINTEL = 5916,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
+ RuntimeAlignedAttributeINTEL = 5939,
IOPipesINTEL = 5943,
BlockingPipesINTEL = 5945,
FPGARegINTEL = 5948,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index af4f06b..234b8a3 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -456,6 +456,7 @@
SpvFunctionParameterAttributeNoCapture = 5,
SpvFunctionParameterAttributeNoWrite = 6,
SpvFunctionParameterAttributeNoReadWrite = 7,
+ SpvFunctionParameterAttributeRuntimeAlignedINTEL = 5940,
SpvFunctionParameterAttributeMax = 0x7fffffff,
} SpvFunctionParameterAttribute;
@@ -564,8 +565,12 @@
SpvDecorationPrefetchINTEL = 5902,
SpvDecorationStallEnableINTEL = 5905,
SpvDecorationFuseLoopsInFunctionINTEL = 5907,
+ SpvDecorationMathOpDSPModeINTEL = 5909,
SpvDecorationAliasScopeINTEL = 5914,
SpvDecorationNoAliasINTEL = 5915,
+ SpvDecorationInitiationIntervalINTEL = 5917,
+ SpvDecorationMaxConcurrencyINTEL = 5918,
+ SpvDecorationPipelineEnableINTEL = 5919,
SpvDecorationBufferLocationINTEL = 5921,
SpvDecorationIOPipeStorageINTEL = 5944,
SpvDecorationFunctionFloatingPointModeINTEL = 6080,
@@ -740,6 +745,8 @@
SpvLoopControlMaxInterleavingINTELShift = 21,
SpvLoopControlSpeculatedIterationsINTELShift = 22,
SpvLoopControlNoFusionINTELShift = 23,
+ SpvLoopControlLoopCountINTELShift = 24,
+ SpvLoopControlMaxReinvocationDelayINTELShift = 25,
SpvLoopControlMax = 0x7fffffff,
} SpvLoopControlShift;
@@ -762,6 +769,8 @@
SpvLoopControlMaxInterleavingINTELMask = 0x00200000,
SpvLoopControlSpeculatedIterationsINTELMask = 0x00400000,
SpvLoopControlNoFusionINTELMask = 0x00800000,
+ SpvLoopControlLoopCountINTELMask = 0x01000000,
+ SpvLoopControlMaxReinvocationDelayINTELMask = 0x02000000,
} SpvLoopControlMask;
typedef enum SpvFunctionControlShift_ {
@@ -1096,10 +1105,13 @@
SpvCapabilityFPGAMemoryAccessesINTEL = 5898,
SpvCapabilityFPGAClusterAttributesINTEL = 5904,
SpvCapabilityLoopFuseINTEL = 5906,
+ SpvCapabilityFPGADSPControlINTEL = 5908,
SpvCapabilityMemoryAccessAliasingINTEL = 5910,
+ SpvCapabilityFPGAInvocationPipeliningAttributesINTEL = 5916,
SpvCapabilityFPGABufferLocationINTEL = 5920,
SpvCapabilityArbitraryPrecisionFixedPointINTEL = 5922,
SpvCapabilityUSMStorageClassesINTEL = 5935,
+ SpvCapabilityRuntimeAlignedAttributeINTEL = 5939,
SpvCapabilityIOPipesINTEL = 5943,
SpvCapabilityBlockingPipesINTEL = 5945,
SpvCapabilityFPGARegINTEL = 5948,
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index b7ec5d7..ef7d122 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -452,6 +452,7 @@
FunctionParameterAttributeNoCapture = 5,
FunctionParameterAttributeNoWrite = 6,
FunctionParameterAttributeNoReadWrite = 7,
+ FunctionParameterAttributeRuntimeAlignedINTEL = 5940,
FunctionParameterAttributeMax = 0x7fffffff,
};
@@ -560,8 +561,12 @@
DecorationPrefetchINTEL = 5902,
DecorationStallEnableINTEL = 5905,
DecorationFuseLoopsInFunctionINTEL = 5907,
+ DecorationMathOpDSPModeINTEL = 5909,
DecorationAliasScopeINTEL = 5914,
DecorationNoAliasINTEL = 5915,
+ DecorationInitiationIntervalINTEL = 5917,
+ DecorationMaxConcurrencyINTEL = 5918,
+ DecorationPipelineEnableINTEL = 5919,
DecorationBufferLocationINTEL = 5921,
DecorationIOPipeStorageINTEL = 5944,
DecorationFunctionFloatingPointModeINTEL = 6080,
@@ -736,6 +741,8 @@
LoopControlMaxInterleavingINTELShift = 21,
LoopControlSpeculatedIterationsINTELShift = 22,
LoopControlNoFusionINTELShift = 23,
+ LoopControlLoopCountINTELShift = 24,
+ LoopControlMaxReinvocationDelayINTELShift = 25,
LoopControlMax = 0x7fffffff,
};
@@ -758,6 +765,8 @@
LoopControlMaxInterleavingINTELMask = 0x00200000,
LoopControlSpeculatedIterationsINTELMask = 0x00400000,
LoopControlNoFusionINTELMask = 0x00800000,
+ LoopControlLoopCountINTELMask = 0x01000000,
+ LoopControlMaxReinvocationDelayINTELMask = 0x02000000,
};
enum FunctionControlShift {
@@ -1092,10 +1101,13 @@
CapabilityFPGAMemoryAccessesINTEL = 5898,
CapabilityFPGAClusterAttributesINTEL = 5904,
CapabilityLoopFuseINTEL = 5906,
+ CapabilityFPGADSPControlINTEL = 5908,
CapabilityMemoryAccessAliasingINTEL = 5910,
+ CapabilityFPGAInvocationPipeliningAttributesINTEL = 5916,
CapabilityFPGABufferLocationINTEL = 5920,
CapabilityArbitraryPrecisionFixedPointINTEL = 5922,
CapabilityUSMStorageClassesINTEL = 5935,
+ CapabilityRuntimeAlignedAttributeINTEL = 5939,
CapabilityIOPipesINTEL = 5943,
CapabilityBlockingPipesINTEL = 5945,
CapabilityFPGARegINTEL = 5948,
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index f0f5871..ab4d211 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -452,6 +452,7 @@
NoCapture = 5,
NoWrite = 6,
NoReadWrite = 7,
+ RuntimeAlignedINTEL = 5940,
Max = 0x7fffffff,
};
@@ -560,8 +561,12 @@
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ MathOpDSPModeINTEL = 5909,
AliasScopeINTEL = 5914,
NoAliasINTEL = 5915,
+ InitiationIntervalINTEL = 5917,
+ MaxConcurrencyINTEL = 5918,
+ PipelineEnableINTEL = 5919,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -736,6 +741,8 @@
MaxInterleavingINTEL = 21,
SpeculatedIterationsINTEL = 22,
NoFusionINTEL = 23,
+ LoopCountINTEL = 24,
+ MaxReinvocationDelayINTEL = 25,
Max = 0x7fffffff,
};
@@ -758,6 +765,8 @@
MaxInterleavingINTEL = 0x00200000,
SpeculatedIterationsINTEL = 0x00400000,
NoFusionINTEL = 0x00800000,
+ LoopCountINTEL = 0x01000000,
+ MaxReinvocationDelayINTEL = 0x02000000,
};
enum class FunctionControlShift : unsigned {
@@ -1092,10 +1101,13 @@
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ FPGADSPControlINTEL = 5908,
MemoryAccessAliasingINTEL = 5910,
+ FPGAInvocationPipeliningAttributesINTEL = 5916,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
+ RuntimeAlignedAttributeINTEL = 5939,
IOPipesINTEL = 5943,
BlockingPipesINTEL = 5945,
FPGARegINTEL = 5948,
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index 466f0b0..5f79390 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -474,7 +474,8 @@
"NoAlias": 4,
"NoCapture": 5,
"NoWrite": 6,
- "NoReadWrite": 7
+ "NoReadWrite": 7,
+ "RuntimeAlignedINTEL": 5940
}
},
{
@@ -586,8 +587,12 @@
"PrefetchINTEL": 5902,
"StallEnableINTEL": 5905,
"FuseLoopsInFunctionINTEL": 5907,
+ "MathOpDSPModeINTEL": 5909,
"AliasScopeINTEL": 5914,
"NoAliasINTEL": 5915,
+ "InitiationIntervalINTEL": 5917,
+ "MaxConcurrencyINTEL": 5918,
+ "PipelineEnableINTEL": 5919,
"BufferLocationINTEL": 5921,
"IOPipeStorageINTEL": 5944,
"FunctionFloatingPointModeINTEL": 6080,
@@ -764,7 +769,9 @@
"LoopCoalesceINTEL": 20,
"MaxInterleavingINTEL": 21,
"SpeculatedIterationsINTEL": 22,
- "NoFusionINTEL": 23
+ "NoFusionINTEL": 23,
+ "LoopCountINTEL": 24,
+ "MaxReinvocationDelayINTEL": 25
}
},
{
@@ -1074,10 +1081,13 @@
"FPGAMemoryAccessesINTEL": 5898,
"FPGAClusterAttributesINTEL": 5904,
"LoopFuseINTEL": 5906,
+ "FPGADSPControlINTEL": 5908,
"MemoryAccessAliasingINTEL": 5910,
+ "FPGAInvocationPipeliningAttributesINTEL": 5916,
"FPGABufferLocationINTEL": 5920,
"ArbitraryPrecisionFixedPointINTEL": 5922,
"USMStorageClassesINTEL": 5935,
+ "RuntimeAlignedAttributeINTEL": 5939,
"IOPipesINTEL": 5943,
"BlockingPipesINTEL": 5945,
"FPGARegINTEL": 5948,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index b763c84..385b94b 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -426,6 +426,7 @@
NoCapture = 5,
NoWrite = 6,
NoReadWrite = 7,
+ RuntimeAlignedINTEL = 5940,
},
Decoration = {
@@ -533,8 +534,12 @@
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ MathOpDSPModeINTEL = 5909,
AliasScopeINTEL = 5914,
NoAliasINTEL = 5915,
+ InitiationIntervalINTEL = 5917,
+ MaxConcurrencyINTEL = 5918,
+ PipelineEnableINTEL = 5919,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -706,6 +711,8 @@
MaxInterleavingINTEL = 21,
SpeculatedIterationsINTEL = 22,
NoFusionINTEL = 23,
+ LoopCountINTEL = 24,
+ MaxReinvocationDelayINTEL = 25,
},
LoopControlMask = {
@@ -727,6 +734,8 @@
MaxInterleavingINTEL = 0x00200000,
SpeculatedIterationsINTEL = 0x00400000,
NoFusionINTEL = 0x00800000,
+ LoopCountINTEL = 0x01000000,
+ MaxReinvocationDelayINTEL = 0x02000000,
},
FunctionControlShift = {
@@ -1054,10 +1063,13 @@
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ FPGADSPControlINTEL = 5908,
MemoryAccessAliasingINTEL = 5910,
+ FPGAInvocationPipeliningAttributesINTEL = 5916,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
+ RuntimeAlignedAttributeINTEL = 5939,
IOPipesINTEL = 5943,
BlockingPipesINTEL = 5945,
FPGARegINTEL = 5948,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index 12e3401..642ffee 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -426,6 +426,7 @@
'NoCapture' : 5,
'NoWrite' : 6,
'NoReadWrite' : 7,
+ 'RuntimeAlignedINTEL' : 5940,
},
'Decoration' : {
@@ -533,8 +534,12 @@
'PrefetchINTEL' : 5902,
'StallEnableINTEL' : 5905,
'FuseLoopsInFunctionINTEL' : 5907,
+ 'MathOpDSPModeINTEL' : 5909,
'AliasScopeINTEL' : 5914,
'NoAliasINTEL' : 5915,
+ 'InitiationIntervalINTEL' : 5917,
+ 'MaxConcurrencyINTEL' : 5918,
+ 'PipelineEnableINTEL' : 5919,
'BufferLocationINTEL' : 5921,
'IOPipeStorageINTEL' : 5944,
'FunctionFloatingPointModeINTEL' : 6080,
@@ -706,6 +711,8 @@
'MaxInterleavingINTEL' : 21,
'SpeculatedIterationsINTEL' : 22,
'NoFusionINTEL' : 23,
+ 'LoopCountINTEL' : 24,
+ 'MaxReinvocationDelayINTEL' : 25,
},
'LoopControlMask' : {
@@ -727,6 +734,8 @@
'MaxInterleavingINTEL' : 0x00200000,
'SpeculatedIterationsINTEL' : 0x00400000,
'NoFusionINTEL' : 0x00800000,
+ 'LoopCountINTEL' : 0x01000000,
+ 'MaxReinvocationDelayINTEL' : 0x02000000,
},
'FunctionControlShift' : {
@@ -1054,10 +1063,13 @@
'FPGAMemoryAccessesINTEL' : 5898,
'FPGAClusterAttributesINTEL' : 5904,
'LoopFuseINTEL' : 5906,
+ 'FPGADSPControlINTEL' : 5908,
'MemoryAccessAliasingINTEL' : 5910,
+ 'FPGAInvocationPipeliningAttributesINTEL' : 5916,
'FPGABufferLocationINTEL' : 5920,
'ArbitraryPrecisionFixedPointINTEL' : 5922,
'USMStorageClassesINTEL' : 5935,
+ 'RuntimeAlignedAttributeINTEL' : 5939,
'IOPipesINTEL' : 5943,
'BlockingPipesINTEL' : 5945,
'FPGARegINTEL' : 5948,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index 6462405..c73acb3 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -453,6 +453,7 @@
NoCapture = 5,
NoWrite = 6,
NoReadWrite = 7,
+ RuntimeAlignedINTEL = 5940,
}
enum Decoration : uint
@@ -561,8 +562,12 @@
PrefetchINTEL = 5902,
StallEnableINTEL = 5905,
FuseLoopsInFunctionINTEL = 5907,
+ MathOpDSPModeINTEL = 5909,
AliasScopeINTEL = 5914,
NoAliasINTEL = 5915,
+ InitiationIntervalINTEL = 5917,
+ MaxConcurrencyINTEL = 5918,
+ PipelineEnableINTEL = 5919,
BufferLocationINTEL = 5921,
IOPipeStorageINTEL = 5944,
FunctionFloatingPointModeINTEL = 6080,
@@ -738,6 +743,8 @@
MaxInterleavingINTEL = 21,
SpeculatedIterationsINTEL = 22,
NoFusionINTEL = 23,
+ LoopCountINTEL = 24,
+ MaxReinvocationDelayINTEL = 25,
}
enum LoopControlMask : uint
@@ -760,6 +767,8 @@
MaxInterleavingINTEL = 0x00200000,
SpeculatedIterationsINTEL = 0x00400000,
NoFusionINTEL = 0x00800000,
+ LoopCountINTEL = 0x01000000,
+ MaxReinvocationDelayINTEL = 0x02000000,
}
enum FunctionControlShift : uint
@@ -1099,10 +1108,13 @@
FPGAMemoryAccessesINTEL = 5898,
FPGAClusterAttributesINTEL = 5904,
LoopFuseINTEL = 5906,
+ FPGADSPControlINTEL = 5908,
MemoryAccessAliasingINTEL = 5910,
+ FPGAInvocationPipeliningAttributesINTEL = 5916,
FPGABufferLocationINTEL = 5920,
ArbitraryPrecisionFixedPointINTEL = 5922,
USMStorageClassesINTEL = 5935,
+ RuntimeAlignedAttributeINTEL = 5939,
IOPipesINTEL = 5943,
BlockingPipesINTEL = 5945,
FPGARegINTEL = 5948,
