commit 7669e05273b30fb2176c715eadc4ae317a6936fd
author Dmitry Sidorov <dmitry.sidorov@intel.com> Thu Nov 05 11:45:16 2020 +0300
committer Dmitry Sidorov <dmitry.sidorov@intel.com> Wed Jan 20 13:14:31 2021 +0300
tree f177f47135648b617e7f506177ffeb6849fccd92
parent d5035de3d314eca0df016e4c0fcf6e6d1b61f50b

Upstream SPV_INTEL_inline_assembly extension

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_inline_assembly.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

include/spirv/unified1/spirv.core.grammar.json

diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index ef03cf6..4e9936b 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -5149,6 +5149,49 @@
       "version" : "None"
     },
     {
+      "opname" : "OpAsmTargetINTEL",
+      "class"  : "@exclude",
+      "opcode" : 5609,
+      "operands" : [
+        { "kind" : "IdResultType" },
+        { "kind" : "IdResult" },
+        { "kind" : "LiteralString", "name" : "'Asm target'" }
+      ],
+      "capabilities" : [ "AsmINTEL" ],
+      "extensions" : [ "SPV_INTEL_inline_assembly" ],
+      "version" : "None"
+    },
+    {
+      "opname" : "OpAsmINTEL",
+      "class"  : "@exclude",
+      "opcode" : 5610,
+      "operands" : [
+        { "kind" : "IdResultType" },
+        { "kind" : "IdResult" },
+        { "kind" : "IdRef", "name" : "'Asm type'" },
+        { "kind" : "IdRef", "name" : "'Target'" },
+        { "kind" : "LiteralString", "name" : "'Asm instructions'" },
+        { "kind" : "LiteralString", "name" : "'Constraints'" }
+      ],
+      "capabilities" : [ "AsmINTEL" ],
+      "extensions" : [ "SPV_INTEL_inline_assembly" ],
+      "version" : "None"
+    },
+    {
+      "opname" : "OpAsmCallINTEL",
+      "class"  : "@exclude",
+      "opcode" : 5611,
+      "operands" : [
+        { "kind" : "IdResultType" },
+        { "kind" : "IdResult" },
+        { "kind" : "IdRef", "name" : "'Asm'" },
+        { "kind" : "IdRef", "quantifier" : "*", "name" : "'Argument 0'" }
+      ],
+      "capabilities" : [ "AsmINTEL" ],
+      "extensions" : [ "SPV_INTEL_inline_assembly" ],
+      "version" : "None"
+    },
+    {
       "opname" : "OpDecorateString",
       "class"  : "Annotation",
       "opcode" : 5632,
@@ -9615,6 +9658,23 @@
           "version" : "None"
         },
         {
+          "enumerant" : "ClobberINTEL",
+          "value" : 5607,
+          "parameters" : [
+            { "kind" : "LiteralString", "name" : "'Register'" }
+          ],
+          "capabilities" : [ "AsmINTEL" ],
+          "extensions" : [ "SPV_INTEL_inline_assembly" ],
+          "version" : "None"
+        },
+        {
+          "enumerant" : "SideEffectsINTEL",
+          "value" : 5608,
+          "capabilities" : [ "AsmINTEL" ],
+          "extensions" : [ "SPV_INTEL_inline_assembly" ],
+          "version" : "None"
+        },
+        {
           "enumerant" : "CounterBuffer",
           "value" : 5634,
           "parameters" : [
@@ -11599,6 +11659,12 @@
           "version" : "None"
         },
         {
+          "enumerant" : "AsmINTEL",
+          "value" : 5606,
+          "extensions" : [ "SPV_INTEL_inline_assembly" ],
+          "version" : "None"
+        },
+        {
           "enumerant" : "IndirectReferencesINTEL",
           "value" : 5604,
           "extensions" : [ "SPV_INTEL_function_pointers" ],