Merge branch 'master' of https://github.com/KhronosGroup/SPIRV-Headers into uniform_group_instructions
diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml
index 6b578a5..3078e77 100644
--- a/include/spirv/spir-v.xml
+++ b/include/spirv/spir-v.xml
@@ -166,13 +166,14 @@
<ids type="enumerant" start="6144" end="6271" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
<ids type="enumerant" start="6272" end="6399" vendor="Huawei" comment="Contact wanghuilong2@xunweitech.com"/>
<ids type="enumerant" start="6400" end="6463" vendor="Intel" comment="Contact ben.ashbaugh@intel.com"/>
+ <ids type="enumerant" start="6464" end="6527" vendor="Mikkosoft Productions" comment="Contact Mikko Rasa, tdb@tdb.fi"/>
<!-- Enumerants to reserve for future use. To get a block, allocate
multiples of 64 starting at the lowest available point in this
block and add a corresponding <ids> tag immediately above. Make
sure to fill in the vendor attribute, and preferably add a contact
person/address in a comment attribute. -->
<!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
- <ids type="enumerant" start="6464" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
+ <ids type="enumerant" start="6528" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<!-- End reservations of enumerants -->
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index 421ed97..29317fd 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -5029,7 +5029,7 @@
"opname" : "OpDemoteToHelperInvocationEXT",
"class" : "Control-Flow",
"opcode" : 5380,
- "capabilities" : [ "DemoteToHelperInvocation" ],
+ "capabilities" : [ "DemoteToHelperInvocationEXT" ],
"version" : "1.6"
},
{
@@ -8551,6 +8551,30 @@
"version" : "None"
},
{
+ "opname" : "OpControlBarrierArriveINTEL",
+ "class" : "Barrier",
+ "opcode" : 6142,
+ "operands" : [
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "IdScope", "name" : "'Memory'" },
+ { "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
+ ],
+ "capabilities" : [ "SplitBarrierINTEL" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpControlBarrierWaitINTEL",
+ "class" : "Barrier",
+ "opcode" : 6143,
+ "operands" : [
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "IdScope", "name" : "'Memory'" },
+ { "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
+ ],
+ "capabilities" : [ "SplitBarrierINTEL" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpGroupIMulKHR",
"class" : "Group",
"opcode" : 6401,
@@ -14003,6 +14027,12 @@
"version" : "None"
},
{
+ "enumerant" : "SplitBarrierINTEL",
+ "value" : 6141,
+ "extensions" : [ "SPV_INTEL_split_barrier" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "GroupUniformArithmeticKHR",
"value" : 6400,
"extensions" : [ "SPV_KHR_uniform_group_instructions"],
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 6c04ae7..eb379a3 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -1087,6 +1087,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
}
@@ -1852,6 +1853,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index 3beb44a..e75bef8 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -1087,6 +1087,7 @@
SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
+ SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMax = 0x7fffffff,
} SpvCapability;
@@ -1850,6 +1851,8 @@
SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
+ SpvOpControlBarrierArriveINTEL = 6142,
+ SpvOpControlBarrierWaitINTEL = 6143,
SpvOpGroupIMulKHR = 6401,
SpvOpGroupFMulKHR = 6402,
SpvOpGroupBitwiseAndKHR = 6403,
@@ -2512,6 +2515,8 @@
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 37b0c3c..0991d3c 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -1083,6 +1083,7 @@
CapabilityOptNoneINTEL = 6094,
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
+ CapabilitySplitBarrierINTEL = 6141,
CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMax = 0x7fffffff,
};
@@ -1846,6 +1847,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
@@ -2508,6 +2511,8 @@
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index bf78446..92a94c1 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -1083,6 +1083,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
Max = 0x7fffffff,
};
@@ -1846,6 +1847,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
@@ -2508,6 +2511,8 @@
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index b0dc71b..aabc32d 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -1065,6 +1065,7 @@
"OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095,
"DebugInfoModuleINTEL": 6114,
+ "SplitBarrierINTEL": 6141,
"GroupUniformArithmeticKHR": 6400
}
},
@@ -1839,6 +1840,8 @@
"OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091,
"OpSpecConstantCompositeContinuedINTEL": 6092,
+ "OpControlBarrierArriveINTEL": 6142,
+ "OpControlBarrierWaitINTEL": 6143,
"OpGroupIMulKHR": 6401,
"OpGroupFMulKHR": 6402,
"OpGroupBitwiseAndKHR": 6403,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index d281562..235f1bf 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -1045,6 +1045,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
},
@@ -1797,6 +1798,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index bda26e3..1c15777 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -1045,6 +1045,7 @@
'OptNoneINTEL' : 6094,
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
+ 'SplitBarrierINTEL' : 6141,
'GroupUniformArithmeticKHR' : 6400,
},
@@ -1797,6 +1798,8 @@
'OpTypeStructContinuedINTEL' : 6090,
'OpConstantCompositeContinuedINTEL' : 6091,
'OpSpecConstantCompositeContinuedINTEL' : 6092,
+ 'OpControlBarrierArriveINTEL' : 6142,
+ 'OpControlBarrierWaitINTEL' : 6143,
'OpGroupIMulKHR' : 6401,
'OpGroupFMulKHR' : 6402,
'OpGroupBitwiseAndKHR' : 6403,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index 0c0792d..5ea5179 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -1090,6 +1090,7 @@
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
GroupUniformArithmeticKHR = 6400,
}
@@ -1855,6 +1856,8 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
