blob: fd12acdd82c19e1076eba98f82f62c1e9329985c [file] [log] [blame]
A8 over A8
14 values (originally 17):
v0 = splat 437F0000 (255)
v1 = splat 3B808081 (0.0039215689)
v2 = load8 arg(0)
v3 = to_f32 v2
v4 = mul_f32 v3 v1
v5 = splat 3F800000 (1)
v6 = fnma_f32 v3 v1 v5
v7 = load8 arg(1)
v8 = to_f32 v7
v9 = mul_f32 v8 v1
v10 = fma_f32 v9 v6 v4
v11 = mul_f32 v10 v0
v12 = round v11
store8 arg(1) v12
6 registers, 14 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3B808081 (0.0039215689)
2 r2 = splat 3F800000 (1)
loop:
3 r3 = load8 arg(0)
4 r3 = to_f32 r3
5 r4 = mul_f32 r3 r1
6 r3 = fnma_f32 r3 r1 r2
7 r5 = load8 arg(1)
8 r5 = to_f32 r5
9 r5 = mul_f32 r5 r1
10 r4 = fma_f32 r5 r3 r4
11 r4 = mul_f32 r4 r0
12 r4 = round r4
13 store8 arg(1) r4
A8 over G8
19 values (originally 24):
v0 = splat 437F0000 (255)
v1 = splat 3D93DD98 (0.0722)
v2 = splat 3F800000 (1)
v3 = splat 3B808081 (0.0039215689)
v4 = load8 arg(0)
v5 = to_f32 v4
v6 = fnma_f32 v5 v3 v2
v7 = load8 arg(1)
v8 = to_f32 v7
v9 = mul_f32 v8 v3
v10 = mul_f32 v9 v6
v11 = mul_f32 v10 v1
v12 = splat 3F371759 (0.71520001)
v13 = fma_f32 v10 v12 v11
v14 = splat 3E59B3D0 (0.21259999)
v15 = fma_f32 v10 v14 v13
v16 = mul_f32 v15 v0
v17 = round v16
store8 arg(1) v17
8 registers, 19 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3D93DD98 (0.0722)
2 r2 = splat 3F800000 (1)
3 r3 = splat 3B808081 (0.0039215689)
4 r4 = splat 3F371759 (0.71520001)
5 r5 = splat 3E59B3D0 (0.21259999)
loop:
6 r6 = load8 arg(0)
7 r6 = to_f32 r6
8 r6 = fnma_f32 r6 r3 r2
9 r7 = load8 arg(1)
10 r7 = to_f32 r7
11 r7 = mul_f32 r7 r3
12 r6 = mul_f32 r7 r6
13 r7 = mul_f32 r6 r1
14 r7 = fma_f32 r6 r4 r7
15 r7 = fma_f32 r6 r5 r7
16 r7 = mul_f32 r7 r0
17 r7 = round r7
18 store8 arg(1) r7
A8 over RGBA_8888
39 values (originally 41):
v0 = splat 437F0000 (255)
v1 = splat 3B808081 (0.0039215689)
v2 = load8 arg(0)
v3 = to_f32 v2
v4 = mul_f32 v3 v1
v5 = splat 3F800000 (1)
v6 = fnma_f32 v3 v1 v5
v7 = load32 arg(1)
v8 = shr_i32 v7 24
v9 = to_f32 v8
v10 = mul_f32 v9 v1
v11 = fma_f32 v10 v6 v4
v12 = mul_f32 v11 v0
v13 = round v12
v14 = shr_i32 v7 16
v15 = splat FF (3.5733111e-43)
v16 = bit_and v15 v14
v17 = to_f32 v16
v18 = mul_f32 v17 v1
v19 = mul_f32 v18 v6
v20 = mul_f32 v19 v0
v21 = round v20
v22 = pack v21 v13 8
v23 = shr_i32 v7 8
v24 = bit_and v15 v23
v25 = to_f32 v24
v26 = mul_f32 v25 v1
v27 = mul_f32 v26 v6
v28 = mul_f32 v27 v0
v29 = round v28
v30 = bit_and v15 v7
v31 = to_f32 v30
v32 = mul_f32 v31 v1
v33 = mul_f32 v32 v6
v34 = mul_f32 v33 v0
v35 = round v34
v36 = pack v35 v29 8
v37 = pack v36 v22 16
store32 arg(1) v37
8 registers, 39 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3B808081 (0.0039215689)
2 r2 = splat 3F800000 (1)
3 r3 = splat FF (3.5733111e-43)
loop:
4 r4 = load8 arg(0)
5 r4 = to_f32 r4
6 r5 = mul_f32 r4 r1
7 r4 = fnma_f32 r4 r1 r2
8 r6 = load32 arg(1)
9 r7 = shr_i32 r6 24
10 r7 = to_f32 r7
11 r7 = mul_f32 r7 r1
12 r5 = fma_f32 r7 r4 r5
13 r5 = mul_f32 r5 r0
14 r5 = round r5
15 r7 = shr_i32 r6 16
16 r7 = bit_and r3 r7
17 r7 = to_f32 r7
18 r7 = mul_f32 r7 r1
19 r7 = mul_f32 r7 r4
20 r7 = mul_f32 r7 r0
21 r7 = round r7
22 r5 = pack r7 r5 8
23 r7 = shr_i32 r6 8
24 r7 = bit_and r3 r7
25 r7 = to_f32 r7
26 r7 = mul_f32 r7 r1
27 r7 = mul_f32 r7 r4
28 r7 = mul_f32 r7 r0
29 r7 = round r7
30 r6 = bit_and r3 r6
31 r6 = to_f32 r6
32 r6 = mul_f32 r6 r1
33 r4 = mul_f32 r6 r4
34 r4 = mul_f32 r4 r0
35 r4 = round r4
36 r7 = pack r4 r7 8
37 r5 = pack r7 r5 16
38 store32 arg(1) r5
G8 over A8
11 values (originally 15):
v0 = splat 437F0000 (255)
v1 = splat 3F800000 (1)
v2 = splat 0 (0)
v3 = splat 3B808081 (0.0039215689)
v4 = load8 arg(1)
v5 = to_f32 v4
v6 = mul_f32 v5 v3
v7 = fma_f32 v6 v2 v1
v8 = mul_f32 v7 v0
v9 = round v8
store8 arg(1) v9
5 registers, 11 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3F800000 (1)
2 r2 = splat 0 (0)
3 r3 = splat 3B808081 (0.0039215689)
loop:
4 r4 = load8 arg(1)
5 r4 = to_f32 r4
6 r4 = mul_f32 r4 r3
7 r4 = fma_f32 r4 r2 r1
8 r4 = mul_f32 r4 r0
9 r4 = round r4
10 store8 arg(1) r4
G8 over G8
19 values (originally 23):
v0 = splat 437F0000 (255)
v1 = splat 3D93DD98 (0.0722)
v2 = splat 3B808081 (0.0039215689)
v3 = load8 arg(0)
v4 = to_f32 v3
v5 = mul_f32 v4 v2
v6 = splat 0 (0)
v7 = load8 arg(1)
v8 = to_f32 v7
v9 = mul_f32 v8 v2
v10 = fma_f32 v9 v6 v5
v11 = mul_f32 v10 v1
v12 = splat 3F371759 (0.71520001)
v13 = fma_f32 v10 v12 v11
v14 = splat 3E59B3D0 (0.21259999)
v15 = fma_f32 v10 v14 v13
v16 = mul_f32 v15 v0
v17 = round v16
store8 arg(1) v17
8 registers, 19 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3D93DD98 (0.0722)
2 r2 = splat 3B808081 (0.0039215689)
3 r3 = splat 0 (0)
4 r4 = splat 3F371759 (0.71520001)
5 r5 = splat 3E59B3D0 (0.21259999)
loop:
6 r6 = load8 arg(0)
7 r6 = to_f32 r6
8 r6 = mul_f32 r6 r2
9 r7 = load8 arg(1)
10 r7 = to_f32 r7
11 r7 = mul_f32 r7 r2
12 r6 = fma_f32 r7 r3 r6
13 r7 = mul_f32 r6 r1
14 r7 = fma_f32 r6 r4 r7
15 r7 = fma_f32 r6 r5 r7
16 r7 = mul_f32 r7 r0
17 r7 = round r7
18 store8 arg(1) r7
G8 over RGBA_8888
39 values (originally 43):
v0 = splat 437F0000 (255)
v1 = splat 3F800000 (1)
v2 = splat 0 (0)
v3 = splat 3B808081 (0.0039215689)
v4 = load32 arg(1)
v5 = shr_i32 v4 24
v6 = to_f32 v5
v7 = mul_f32 v6 v3
v8 = fma_f32 v7 v2 v1
v9 = mul_f32 v8 v0
v10 = round v9
v11 = load8 arg(0)
v12 = to_f32 v11
v13 = mul_f32 v12 v3
v14 = shr_i32 v4 16
v15 = splat FF (3.5733111e-43)
v16 = bit_and v15 v14
v17 = to_f32 v16
v18 = mul_f32 v17 v3
v19 = fma_f32 v18 v2 v13
v20 = mul_f32 v19 v0
v21 = round v20
v22 = pack v21 v10 8
v23 = shr_i32 v4 8
v24 = bit_and v15 v23
v25 = to_f32 v24
v26 = mul_f32 v25 v3
v27 = fma_f32 v26 v2 v13
v28 = mul_f32 v27 v0
v29 = round v28
v30 = bit_and v15 v4
v31 = to_f32 v30
v32 = mul_f32 v31 v3
v33 = fma_f32 v32 v2 v13
v34 = mul_f32 v33 v0
v35 = round v34
v36 = pack v35 v29 8
v37 = pack v36 v22 16
store32 arg(1) v37
9 registers, 39 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3F800000 (1)
2 r2 = splat 0 (0)
3 r3 = splat 3B808081 (0.0039215689)
4 r4 = splat FF (3.5733111e-43)
loop:
5 r5 = load32 arg(1)
6 r6 = shr_i32 r5 24
7 r6 = to_f32 r6
8 r6 = mul_f32 r6 r3
9 r6 = fma_f32 r6 r2 r1
10 r6 = mul_f32 r6 r0
11 r6 = round r6
12 r7 = load8 arg(0)
13 r7 = to_f32 r7
14 r7 = mul_f32 r7 r3
15 r8 = shr_i32 r5 16
16 r8 = bit_and r4 r8
17 r8 = to_f32 r8
18 r8 = mul_f32 r8 r3
19 r8 = fma_f32 r8 r2 r7
20 r8 = mul_f32 r8 r0
21 r8 = round r8
22 r6 = pack r8 r6 8
23 r8 = shr_i32 r5 8
24 r8 = bit_and r4 r8
25 r8 = to_f32 r8
26 r8 = mul_f32 r8 r3
27 r8 = fma_f32 r8 r2 r7
28 r8 = mul_f32 r8 r0
29 r8 = round r8
30 r5 = bit_and r4 r5
31 r5 = to_f32 r5
32 r5 = mul_f32 r5 r3
33 r7 = fma_f32 r5 r2 r7
34 r7 = mul_f32 r7 r0
35 r7 = round r7
36 r8 = pack r7 r8 8
37 r6 = pack r8 r6 16
38 store32 arg(1) r6
RGBA_8888 over A8
15 values (originally 33):
v0 = splat 437F0000 (255)
v1 = splat 3B808081 (0.0039215689)
v2 = load32 arg(0)
v3 = shr_i32 v2 24
v4 = to_f32 v3
v5 = mul_f32 v4 v1
v6 = splat 3F800000 (1)
v7 = fnma_f32 v4 v1 v6
v8 = load8 arg(1)
v9 = to_f32 v8
v10 = mul_f32 v9 v1
v11 = fma_f32 v10 v7 v5
v12 = mul_f32 v11 v0
v13 = round v12
store8 arg(1) v13
6 registers, 15 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3B808081 (0.0039215689)
2 r2 = splat 3F800000 (1)
loop:
3 r3 = load32 arg(0)
4 r3 = shr_i32 r3 24
5 r3 = to_f32 r3
6 r4 = mul_f32 r3 r1
7 r3 = fnma_f32 r3 r1 r2
8 r5 = load8 arg(1)
9 r5 = to_f32 r5
10 r5 = mul_f32 r5 r1
11 r4 = fma_f32 r5 r3 r4
12 r4 = mul_f32 r4 r0
13 r4 = round r4
14 store8 arg(1) r4
RGBA_8888 over G8
34 values (originally 39):
v0 = splat 437F0000 (255)
v1 = splat 3D93DD98 (0.0722)
v2 = splat 3B808081 (0.0039215689)
v3 = load32 arg(0)
v4 = shr_i32 v3 16
v5 = splat FF (3.5733111e-43)
v6 = bit_and v5 v4
v7 = to_f32 v6
v8 = mul_f32 v7 v2
v9 = splat 3F800000 (1)
v10 = shr_i32 v3 24
v11 = to_f32 v10
v12 = fnma_f32 v11 v2 v9
v13 = load8 arg(1)
v14 = to_f32 v13
v15 = mul_f32 v14 v2
v16 = fma_f32 v15 v12 v8
v17 = mul_f32 v16 v1
v18 = splat 3F371759 (0.71520001)
v19 = shr_i32 v3 8
v20 = bit_and v5 v19
v21 = to_f32 v20
v22 = mul_f32 v21 v2
v23 = fma_f32 v15 v12 v22
v24 = fma_f32 v23 v18 v17
v25 = splat 3E59B3D0 (0.21259999)
v26 = bit_and v5 v3
v27 = to_f32 v26
v28 = mul_f32 v27 v2
v29 = fma_f32 v15 v12 v28
v30 = fma_f32 v29 v25 v24
v31 = mul_f32 v30 v0
v32 = round v31
store8 arg(1) v32
12 registers, 34 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3D93DD98 (0.0722)
2 r2 = splat 3B808081 (0.0039215689)
3 r3 = splat FF (3.5733111e-43)
4 r4 = splat 3F800000 (1)
5 r5 = splat 3F371759 (0.71520001)
6 r6 = splat 3E59B3D0 (0.21259999)
loop:
7 r7 = load32 arg(0)
8 r8 = shr_i32 r7 16
9 r8 = bit_and r3 r8
10 r8 = to_f32 r8
11 r8 = mul_f32 r8 r2
12 r9 = shr_i32 r7 24
13 r9 = to_f32 r9
14 r9 = fnma_f32 r9 r2 r4
15 r10 = load8 arg(1)
16 r10 = to_f32 r10
17 r10 = mul_f32 r10 r2
18 r8 = fma_f32 r10 r9 r8
19 r8 = mul_f32 r8 r1
20 r11 = shr_i32 r7 8
21 r11 = bit_and r3 r11
22 r11 = to_f32 r11
23 r11 = mul_f32 r11 r2
24 r11 = fma_f32 r10 r9 r11
25 r8 = fma_f32 r11 r5 r8
26 r7 = bit_and r3 r7
27 r7 = to_f32 r7
28 r7 = mul_f32 r7 r2
29 r7 = fma_f32 r10 r9 r7
30 r8 = fma_f32 r7 r6 r8
31 r8 = mul_f32 r8 r0
32 r8 = round r8
33 store8 arg(1) r8
RGBA_8888 over RGBA_8888
51 values (originally 55):
v0 = splat 437F0000 (255)
v1 = splat 3B808081 (0.0039215689)
v2 = load32 arg(0)
v3 = shr_i32 v2 24
v4 = to_f32 v3
v5 = mul_f32 v4 v1
v6 = splat 3F800000 (1)
v7 = fnma_f32 v4 v1 v6
v8 = load32 arg(1)
v9 = shr_i32 v8 24
v10 = to_f32 v9
v11 = mul_f32 v10 v1
v12 = fma_f32 v11 v7 v5
v13 = mul_f32 v12 v0
v14 = round v13
v15 = shr_i32 v2 16
v16 = splat FF (3.5733111e-43)
v17 = bit_and v16 v15
v18 = to_f32 v17
v19 = mul_f32 v18 v1
v20 = shr_i32 v8 16
v21 = bit_and v16 v20
v22 = to_f32 v21
v23 = mul_f32 v22 v1
v24 = fma_f32 v23 v7 v19
v25 = mul_f32 v24 v0
v26 = round v25
v27 = pack v26 v14 8
v28 = shr_i32 v2 8
v29 = bit_and v16 v28
v30 = to_f32 v29
v31 = mul_f32 v30 v1
v32 = shr_i32 v8 8
v33 = bit_and v16 v32
v34 = to_f32 v33
v35 = mul_f32 v34 v1
v36 = fma_f32 v35 v7 v31
v37 = mul_f32 v36 v0
v38 = round v37
v39 = bit_and v16 v2
v40 = to_f32 v39
v41 = mul_f32 v40 v1
v42 = bit_and v16 v8
v43 = to_f32 v42
v44 = mul_f32 v43 v1
v45 = fma_f32 v44 v7 v41
v46 = mul_f32 v45 v0
v47 = round v46
v48 = pack v47 v38 8
v49 = pack v48 v27 16
store32 arg(1) v49
10 registers, 51 instructions:
0 r0 = splat 437F0000 (255)
1 r1 = splat 3B808081 (0.0039215689)
2 r2 = splat 3F800000 (1)
3 r3 = splat FF (3.5733111e-43)
loop:
4 r4 = load32 arg(0)
5 r5 = shr_i32 r4 24
6 r5 = to_f32 r5
7 r6 = mul_f32 r5 r1
8 r5 = fnma_f32 r5 r1 r2
9 r7 = load32 arg(1)
10 r8 = shr_i32 r7 24
11 r8 = to_f32 r8
12 r8 = mul_f32 r8 r1
13 r6 = fma_f32 r8 r5 r6
14 r6 = mul_f32 r6 r0
15 r6 = round r6
16 r8 = shr_i32 r4 16
17 r8 = bit_and r3 r8
18 r8 = to_f32 r8
19 r8 = mul_f32 r8 r1
20 r9 = shr_i32 r7 16
21 r9 = bit_and r3 r9
22 r9 = to_f32 r9
23 r9 = mul_f32 r9 r1
24 r8 = fma_f32 r9 r5 r8
25 r8 = mul_f32 r8 r0
26 r8 = round r8
27 r6 = pack r8 r6 8
28 r8 = shr_i32 r4 8
29 r8 = bit_and r3 r8
30 r8 = to_f32 r8
31 r8 = mul_f32 r8 r1
32 r9 = shr_i32 r7 8
33 r9 = bit_and r3 r9
34 r9 = to_f32 r9
35 r9 = mul_f32 r9 r1
36 r8 = fma_f32 r9 r5 r8
37 r8 = mul_f32 r8 r0
38 r8 = round r8
39 r4 = bit_and r3 r4
40 r4 = to_f32 r4
41 r4 = mul_f32 r4 r1
42 r7 = bit_and r3 r7
43 r7 = to_f32 r7
44 r7 = mul_f32 r7 r1
45 r4 = fma_f32 r7 r5 r4
46 r4 = mul_f32 r4 r0
47 r4 = round r4
48 r8 = pack r4 r8 8
49 r6 = pack r8 r6 16
50 store32 arg(1) r6
I32 (Naive) 8888 over 8888
33 values (originally 33):
v0 = load32 arg(0)
v1 = shr_i32 v0 24
v2 = splat 100 (3.5873241e-43)
v3 = sub_i32 v2 v1
v4 = load32 arg(1)
v5 = shr_i32 v4 24
v6 = mul_i32 v5 v3
v7 = shr_i32 v6 8
v8 = add_i32 v1 v7
v9 = shr_i32 v4 16
v10 = splat FF (3.5733111e-43)
v11 = bit_and v10 v9
v12 = mul_i32 v11 v3
v13 = shr_i32 v12 8
v14 = shr_i32 v0 16
v15 = bit_and v10 v14
v16 = add_i32 v15 v13
v17 = pack v16 v8 8
v18 = shr_i32 v4 8
v19 = bit_and v10 v18
v20 = mul_i32 v19 v3
v21 = shr_i32 v20 8
v22 = shr_i32 v0 8
v23 = bit_and v10 v22
v24 = add_i32 v23 v21
v25 = bit_and v10 v4
v26 = mul_i32 v25 v3
v27 = shr_i32 v26 8
v28 = bit_and v10 v0
v29 = add_i32 v28 v27
v30 = pack v29 v24 8
v31 = pack v30 v17 16
store32 arg(1) v31
8 registers, 33 instructions:
0 r0 = splat 100 (3.5873241e-43)
1 r1 = splat FF (3.5733111e-43)
loop:
2 r2 = load32 arg(0)
3 r3 = shr_i32 r2 24
4 r4 = sub_i32 r0 r3
5 r5 = load32 arg(1)
6 r6 = shr_i32 r5 24
7 r6 = mul_i32 r6 r4
8 r6 = shr_i32 r6 8
9 r6 = add_i32 r3 r6
10 r3 = shr_i32 r5 16
11 r3 = bit_and r1 r3
12 r3 = mul_i32 r3 r4
13 r3 = shr_i32 r3 8
14 r7 = shr_i32 r2 16
15 r7 = bit_and r1 r7
16 r3 = add_i32 r7 r3
17 r6 = pack r3 r6 8
18 r3 = shr_i32 r5 8
19 r3 = bit_and r1 r3
20 r3 = mul_i32 r3 r4
21 r3 = shr_i32 r3 8
22 r7 = shr_i32 r2 8
23 r7 = bit_and r1 r7
24 r3 = add_i32 r7 r3
25 r5 = bit_and r1 r5
26 r4 = mul_i32 r5 r4
27 r4 = shr_i32 r4 8
28 r2 = bit_and r1 r2
29 r4 = add_i32 r2 r4
30 r3 = pack r4 r3 8
31 r6 = pack r3 r6 16
32 store32 arg(1) r6
23 values (originally 23):
v0 = load32 arg(1)
v1 = shr_i32 v0 24
v2 = load32 arg(0)
v3 = shr_i32 v2 24
v4 = add_i32 v3 v1
v5 = shr_i32 v0 16
v6 = splat FF (3.5733111e-43)
v7 = bit_and v6 v5
v8 = shr_i32 v2 16
v9 = bit_and v6 v8
v10 = add_i32 v9 v7
v11 = pack v10 v4 8
v12 = shr_i32 v0 8
v13 = bit_and v6 v12
v14 = shr_i32 v2 8
v15 = bit_and v6 v14
v16 = add_i32 v15 v13
v17 = bit_and v6 v0
v18 = bit_and v6 v2
v19 = add_i32 v18 v17
v20 = pack v19 v16 8
v21 = pack v20 v11 16
store32 arg(1) v21
6 registers, 23 instructions:
0 r0 = splat FF (3.5733111e-43)
loop:
1 r1 = load32 arg(1)
2 r2 = shr_i32 r1 24
3 r3 = load32 arg(0)
4 r4 = shr_i32 r3 24
5 r2 = add_i32 r4 r2
6 r4 = shr_i32 r1 16
7 r4 = bit_and r0 r4
8 r5 = shr_i32 r3 16
9 r5 = bit_and r0 r5
10 r4 = add_i32 r5 r4
11 r2 = pack r4 r2 8
12 r4 = shr_i32 r1 8
13 r4 = bit_and r0 r4
14 r5 = shr_i32 r3 8
15 r5 = bit_and r0 r5
16 r4 = add_i32 r5 r4
17 r1 = bit_and r0 r1
18 r3 = bit_and r0 r3
19 r1 = add_i32 r3 r1
20 r4 = pack r1 r4 8
21 r2 = pack r4 r2 16
22 store32 arg(1) r2