)]}'
{
  "commit": "07311aeba0d2f57b60de97f000c92cc5a798fbbc",
  "tree": "043ee02cfad888d2b28b3d025db111277daf4f71",
  "parents": [
    "3b4af2e20bf50e222c2cfd5a22b5d9a4e70d2b8b"
  ],
  "author": {
    "name": "luigi-rosso",
    "email": "hello@rive.app",
    "time": "Thu Oct 01 22:27:30 2026 +0000"
  },
  "committer": {
    "name": "luigi-rosso",
    "email": "hello@rive.app",
    "time": "Thu Oct 01 22:27:30 2026 +0000"
  },
  "message": "feat(artemis): native test lane at 120 Hz and VRR (#14523) 37aef8611c\n* feat(artemis): native test lane at 120 Hz and VRR\n\n* fix(artemis): refresh keeps the present mode\u0027s pacing, timing only on Artemis, no blocking refresh probe and no leaks\n\n* chore(artemis): the tool wiring filters name both lanes\n\nCo-authored-by: Luigi Rosso \u003cluigi-rosso@users.noreply.github.com\u003e\n",
  "tree_diff": [
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}