base: disable SIMD on 32-bit (not 64-bit) x86
Fixes #145
diff --git a/internal/cgen/base/fundamental-public.h b/internal/cgen/base/fundamental-public.h
index 3bc9bd8..1b6396e 100644
--- a/internal/cgen/base/fundamental-public.h
+++ b/internal/cgen/base/fundamental-public.h
@@ -214,7 +214,7 @@
#if defined(__BMI2__)
return true;
#else
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
// GCC defines these macros but MSVC does not.
// - bit_BMI2 = (1 << 8)
const unsigned int bmi2_ebx7 = 0x00000100;
@@ -238,7 +238,7 @@
#else
#error "WUFFS_BASE__CPU_ARCH__ETC combined with an unsupported compiler"
#endif // defined(__GNUC__); defined(_MSC_VER)
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
return false;
#endif // defined(__BMI2__)
}
@@ -248,7 +248,7 @@
#if defined(__PCLMUL__) && defined(__POPCNT__) && defined(__SSE4_2__)
return true;
#else
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
// GCC defines these macros but MSVC does not.
// - bit_PCLMUL = (1 << 1)
// - bit_POPCNT = (1 << 23)
@@ -274,7 +274,7 @@
#else
#error "WUFFS_BASE__CPU_ARCH__ETC combined with an unsupported compiler"
#endif // defined(__GNUC__); defined(_MSC_VER)
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
return false;
#endif // defined(__PCLMUL__) && defined(__POPCNT__) && defined(__SSE4_2__)
}
diff --git a/internal/cgen/base/pixconv-submodule-regular.c b/internal/cgen/base/pixconv-submodule-regular.c
index 2844795..f8b5891 100644
--- a/internal/cgen/base/pixconv-submodule-regular.c
+++ b/internal/cgen/base/pixconv-submodule-regular.c
@@ -10,7 +10,7 @@
// ---------------- Pixel Swizzler
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42(uint8_t* dst_ptr,
@@ -45,7 +45,7 @@
size_t dst_palette_len,
const uint8_t* src_ptr,
size_t src_len);
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// --------
@@ -881,7 +881,7 @@
}
// ‼ WUFFS MULTI-FILE SECTION +x86_sse42
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42(uint8_t* dst_ptr,
@@ -925,7 +925,7 @@
}
return len;
}
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// ‼ WUFFS MULTI-FILE SECTION -x86_sse42
static uint64_t //
@@ -3593,7 +3593,7 @@
}
// ‼ WUFFS MULTI-FILE SECTION +x86_sse42
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42(uint8_t* dst_ptr,
@@ -3699,7 +3699,7 @@
return len;
}
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// ‼ WUFFS MULTI-FILE SECTION -x86_sse42
static uint64_t //
@@ -4457,7 +4457,7 @@
}
// ‼ WUFFS MULTI-FILE SECTION +x86_sse42
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_xxxx__y__x86_sse42(uint8_t* dst_ptr,
@@ -4504,7 +4504,7 @@
return len;
}
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// ‼ WUFFS MULTI-FILE SECTION -x86_sse42
static uint64_t //
@@ -4825,7 +4825,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__RGBA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__RGBX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_xxxx__y__x86_sse42;
}
@@ -5296,7 +5296,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__BGRA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__BGRX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42;
}
@@ -5314,7 +5314,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__RGBA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__RGBX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__rgb__x86_sse42;
}
@@ -5394,7 +5394,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_NONPREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
@@ -5589,7 +5589,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
@@ -5658,7 +5658,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__BGRA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__BGRX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__rgb__x86_sse42;
}
@@ -5675,7 +5675,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__RGBA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__RGBX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42;
}
@@ -5714,7 +5714,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_NONPREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
@@ -5830,7 +5830,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_PREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
diff --git a/release/c/wuffs-unsupported-snapshot.c b/release/c/wuffs-unsupported-snapshot.c
index 3ddb728..360d277 100644
--- a/release/c/wuffs-unsupported-snapshot.c
+++ b/release/c/wuffs-unsupported-snapshot.c
@@ -270,7 +270,7 @@
#if defined(__BMI2__)
return true;
#else
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
// GCC defines these macros but MSVC does not.
// - bit_BMI2 = (1 << 8)
const unsigned int bmi2_ebx7 = 0x00000100;
@@ -294,7 +294,7 @@
#else
#error "WUFFS_BASE__CPU_ARCH__ETC combined with an unsupported compiler"
#endif // defined(__GNUC__); defined(_MSC_VER)
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
return false;
#endif // defined(__BMI2__)
}
@@ -304,7 +304,7 @@
#if defined(__PCLMUL__) && defined(__POPCNT__) && defined(__SSE4_2__)
return true;
#else
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
// GCC defines these macros but MSVC does not.
// - bit_PCLMUL = (1 << 1)
// - bit_POPCNT = (1 << 23)
@@ -330,7 +330,7 @@
#else
#error "WUFFS_BASE__CPU_ARCH__ETC combined with an unsupported compiler"
#endif // defined(__GNUC__); defined(_MSC_VER)
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
return false;
#endif // defined(__PCLMUL__) && defined(__POPCNT__) && defined(__SSE4_2__)
}
@@ -21042,7 +21042,7 @@
// ---------------- Pixel Swizzler
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42(uint8_t* dst_ptr,
@@ -21077,7 +21077,7 @@
size_t dst_palette_len,
const uint8_t* src_ptr,
size_t src_len);
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// --------
@@ -21913,7 +21913,7 @@
}
// ‼ WUFFS MULTI-FILE SECTION +x86_sse42
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42(uint8_t* dst_ptr,
@@ -21957,7 +21957,7 @@
}
return len;
}
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// ‼ WUFFS MULTI-FILE SECTION -x86_sse42
static uint64_t //
@@ -24625,7 +24625,7 @@
}
// ‼ WUFFS MULTI-FILE SECTION +x86_sse42
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42(uint8_t* dst_ptr,
@@ -24731,7 +24731,7 @@
return len;
}
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// ‼ WUFFS MULTI-FILE SECTION -x86_sse42
static uint64_t //
@@ -25489,7 +25489,7 @@
}
// ‼ WUFFS MULTI-FILE SECTION +x86_sse42
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
WUFFS_BASE__MAYBE_ATTRIBUTE_TARGET("pclmul,popcnt,sse4.2")
static uint64_t //
wuffs_private_impl__swizzle_xxxx__y__x86_sse42(uint8_t* dst_ptr,
@@ -25536,7 +25536,7 @@
return len;
}
-#endif // defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
// ‼ WUFFS MULTI-FILE SECTION -x86_sse42
static uint64_t //
@@ -25857,7 +25857,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__RGBA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__RGBX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_xxxx__y__x86_sse42;
}
@@ -26328,7 +26328,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__BGRA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__BGRX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42;
}
@@ -26346,7 +26346,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__RGBA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__RGBX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__rgb__x86_sse42;
}
@@ -26426,7 +26426,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_NONPREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
@@ -26621,7 +26621,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
@@ -26690,7 +26690,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__BGRA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__BGRX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__rgb__x86_sse42;
}
@@ -26707,7 +26707,7 @@
case WUFFS_BASE__PIXEL_FORMAT__RGBA_PREMUL:
case WUFFS_BASE__PIXEL_FORMAT__RGBA_BINARY:
case WUFFS_BASE__PIXEL_FORMAT__RGBX:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_bgrw__bgr__x86_sse42;
}
@@ -26746,7 +26746,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_NONPREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
@@ -26862,7 +26862,7 @@
case WUFFS_BASE__PIXEL_FORMAT__BGRA_PREMUL:
switch (blend) {
case WUFFS_BASE__PIXEL_BLEND__SRC:
-#if defined(WUFFS_BASE__CPU_ARCH__X86_FAMILY)
+#if defined(WUFFS_BASE__CPU_ARCH__X86_64)
if (wuffs_base__cpu_arch__have_x86_sse42()) {
return wuffs_private_impl__swizzle_swap_rgbx_bgrx__x86_sse42;
}
