Have "SSE42 capable" also include PCLMUL
diff --git a/internal/cgen/base/fundamental-public.h b/internal/cgen/base/fundamental-public.h
index bc47e82..d99070e 100644
--- a/internal/cgen/base/fundamental-public.h
+++ b/internal/cgen/base/fundamental-public.h
@@ -70,7 +70,8 @@
// WUFFS_BASE__CPU_ARCH__X86_64__ETC are bits returned by
// wuffs_base__cpu_arch__x86_64__capabilities.
-// - "SSE42" means all of SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and POPCNT.
+// - "SSE42" means all of SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, PCLMUL and
+// POPCNT.
// - "AVX2" means all of AVX and AVX2.
// - "AVX512ETC" is reserved, pending need. Note that AVX-512 consists of
// multiple extensions that may be implemented independently.
@@ -87,7 +88,7 @@
unsigned int ecx1 = 0;
unsigned int edx1 = 0;
if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {
- const unsigned int sse42_ecx1 = bit_SSE4_2 | bit_POPCNT;
+ const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;
if ((ecx1 & sse42_ecx1) == sse42_ecx1) {
ret |= WUFFS_BASE__CPU_ARCH__X86_64__SSE42;
}
@@ -118,7 +119,7 @@
unsigned int ecx1 = 0;
unsigned int edx1 = 0;
if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {
- const unsigned int sse42_ecx1 = bit_SSE4_2 | bit_POPCNT;
+ const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;
return (ecx1 & sse42_ecx1) == sse42_ecx1;
}
#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
diff --git a/internal/cgen/data/data.go b/internal/cgen/data/data.go
index 8357d53..80f0834 100644
--- a/internal/cgen/data/data.go
+++ b/internal/cgen/data/data.go
@@ -58,8 +58,8 @@
"" +
"// --------\n\n// Define WUFFS_CONFIG__STATIC_FUNCTIONS to make all of Wuffs' functions have\n// static storage. The motivation is discussed in the \"ALLOW STATIC\n// IMPLEMENTATION\" section of\n// https://raw.githubusercontent.com/nothings/stb/master/docs/stb_howto.txt\n#if defined(WUFFS_CONFIG__STATIC_FUNCTIONS)\n#define WUFFS_BASE__MAYBE_STATIC static\n#else\n#define WUFFS_BASE__MAYBE_STATIC\n#endif // defined(WUFFS_CONFIG__STATIC_FUNCTIONS)\n\n" +
"" +
- "// ---------------- CPU Architecture\n\n// WUFFS_BASE__CPU_ARCH__X86_64__ETC are bits returned by\n// wuffs_base__cpu_arch__x86_64__capabilities.\n// - \"SSE42\" means all of SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and POPCNT.\n// - \"AVX2\" means all of AVX and AVX2.\n// - \"AVX512ETC\" is reserved, pending need. Note that AVX-512 consists of\n// multiple extensions that may be implemented independently.\n#define WUFFS_BASE__CPU_ARCH__X86_64__SSE42 0x01\n#define WUFFS_BASE__CPU_ARCH__X86_64__AVX2 0x02\n\nstatic inline uint32_t //\nwuffs_base__cpu_arch__x86_64__capabilities() {\n#if defined(WUFFS_BASE__CPU_ARCH__X86_64)\n uint32_t ret = 0;\n\n unsigned int eax1 = 0;\n unsigned int ebx1 = 0;\n unsigned int ecx1 = 0;\n unsigned int edx1 = 0;\n if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {\n const unsigned int sse42_ecx1 = bit_SSE4_2 | bit_POPCNT;\n if ((ecx1 & sse42_ecx1) == sse42_ecx1) {\n ret |= WUFFS_BASE__CPU_ARCH__X86_64__SSE42;\n }\n }\n\n unsigned int eax7 = 0;\n unsigned int ebx7 = 0;\n unsigned int ecx7 = " +
- "0;\n unsigned int edx7 = 0;\n if (__get_cpuid_count(7, 0, &eax7, &ebx7, &ecx7, &edx7)) {\n const unsigned int avx256_ebx7 = bit_AVX2;\n if ((ebx7 & avx256_ebx7) == avx256_ebx7) {\n ret |= WUFFS_BASE__CPU_ARCH__X86_64__AVX2;\n }\n }\n\n return ret;\n#else\n return 0;\n#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)\n}\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_sse42() {\n#if defined(WUFFS_BASE__CPU_ARCH__X86_64)\n unsigned int eax1 = 0;\n unsigned int ebx1 = 0;\n unsigned int ecx1 = 0;\n unsigned int edx1 = 0;\n if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {\n const unsigned int sse42_ecx1 = bit_SSE4_2 | bit_POPCNT;\n return (ecx1 & sse42_ecx1) == sse42_ecx1;\n }\n#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)\n return false;\n}\n\n" +
+ "// ---------------- CPU Architecture\n\n// WUFFS_BASE__CPU_ARCH__X86_64__ETC are bits returned by\n// wuffs_base__cpu_arch__x86_64__capabilities.\n// - \"SSE42\" means all of SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, PCLMUL and\n// POPCNT.\n// - \"AVX2\" means all of AVX and AVX2.\n// - \"AVX512ETC\" is reserved, pending need. Note that AVX-512 consists of\n// multiple extensions that may be implemented independently.\n#define WUFFS_BASE__CPU_ARCH__X86_64__SSE42 0x01\n#define WUFFS_BASE__CPU_ARCH__X86_64__AVX2 0x02\n\nstatic inline uint32_t //\nwuffs_base__cpu_arch__x86_64__capabilities() {\n#if defined(WUFFS_BASE__CPU_ARCH__X86_64)\n uint32_t ret = 0;\n\n unsigned int eax1 = 0;\n unsigned int ebx1 = 0;\n unsigned int ecx1 = 0;\n unsigned int edx1 = 0;\n if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {\n const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;\n if ((ecx1 & sse42_ecx1) == sse42_ecx1) {\n ret |= WUFFS_BASE__CPU_ARCH__X86_64__SSE42;\n }\n }\n\n unsigned int eax7 = 0;\n unsigned int ebx7 =" +
+ " 0;\n unsigned int ecx7 = 0;\n unsigned int edx7 = 0;\n if (__get_cpuid_count(7, 0, &eax7, &ebx7, &ecx7, &edx7)) {\n const unsigned int avx256_ebx7 = bit_AVX2;\n if ((ebx7 & avx256_ebx7) == avx256_ebx7) {\n ret |= WUFFS_BASE__CPU_ARCH__X86_64__AVX2;\n }\n }\n\n return ret;\n#else\n return 0;\n#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)\n}\n\nstatic inline bool //\nwuffs_base__cpu_arch__have_sse42() {\n#if defined(WUFFS_BASE__CPU_ARCH__X86_64)\n unsigned int eax1 = 0;\n unsigned int ebx1 = 0;\n unsigned int ecx1 = 0;\n unsigned int edx1 = 0;\n if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {\n const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;\n return (ecx1 & sse42_ecx1) == sse42_ecx1;\n }\n#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)\n return false;\n}\n\n" +
"" +
"// ---------------- Fundamentals\n\n// Wuffs assumes that:\n// - converting a uint32_t to a size_t will never overflow.\n// - converting a size_t to a uint64_t will never overflow.\n#ifdef __WORDSIZE\n#if (__WORDSIZE != 32) && (__WORDSIZE != 64)\n#error \"Wuffs requires a word size of either 32 or 64 bits\"\n#endif\n#endif\n\n#if defined(__clang__)\n#define WUFFS_BASE__POTENTIALLY_UNUSED_FIELD __attribute__((unused))\n#else\n#define WUFFS_BASE__POTENTIALLY_UNUSED_FIELD\n#endif\n\n// Clang also defines \"__GNUC__\".\n#if defined(__GNUC__)\n#define WUFFS_BASE__POTENTIALLY_UNUSED __attribute__((unused))\n#define WUFFS_BASE__WARN_UNUSED_RESULT __attribute__((warn_unused_result))\n#else\n#define WUFFS_BASE__POTENTIALLY_UNUSED\n#define WUFFS_BASE__WARN_UNUSED_RESULT\n#endif\n\n" +
"" +
diff --git a/release/c/wuffs-unsupported-snapshot.c b/release/c/wuffs-unsupported-snapshot.c
index 8cb8e3a..a167986 100644
--- a/release/c/wuffs-unsupported-snapshot.c
+++ b/release/c/wuffs-unsupported-snapshot.c
@@ -104,7 +104,8 @@
// WUFFS_BASE__CPU_ARCH__X86_64__ETC are bits returned by
// wuffs_base__cpu_arch__x86_64__capabilities.
-// - "SSE42" means all of SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and POPCNT.
+// - "SSE42" means all of SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, PCLMUL and
+// POPCNT.
// - "AVX2" means all of AVX and AVX2.
// - "AVX512ETC" is reserved, pending need. Note that AVX-512 consists of
// multiple extensions that may be implemented independently.
@@ -121,7 +122,7 @@
unsigned int ecx1 = 0;
unsigned int edx1 = 0;
if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {
- const unsigned int sse42_ecx1 = bit_SSE4_2 | bit_POPCNT;
+ const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;
if ((ecx1 & sse42_ecx1) == sse42_ecx1) {
ret |= WUFFS_BASE__CPU_ARCH__X86_64__SSE42;
}
@@ -152,7 +153,7 @@
unsigned int ecx1 = 0;
unsigned int edx1 = 0;
if (__get_cpuid(1, &eax1, &ebx1, &ecx1, &edx1)) {
- const unsigned int sse42_ecx1 = bit_SSE4_2 | bit_POPCNT;
+ const unsigned int sse42_ecx1 = bit_PCLMUL | bit_POPCNT | bit_SSE4_2;
return (ecx1 & sse42_ecx1) == sse42_ecx1;
}
#endif // defined(WUFFS_BASE__CPU_ARCH__X86_64)
