diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 54e41a2..d04c1b4 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -164,6 +164,10 @@
             SampleInterlockUnorderedEXT = 5369,
             ShadingRateInterlockOrderedEXT = 5370,
             ShadingRateInterlockUnorderedEXT = 5371,
+            MaxWorkgroupSizeINTEL = 5893,
+            MaxWorkDimINTEL = 5894,
+            NoGlobalOffsetINTEL = 5895,
+            NumSIMDWorkitemsINTEL = 5896,
         }
 
         public enum StorageClass
@@ -482,6 +486,18 @@
             HlslSemanticGOOGLE = 5635,
             UserSemantic = 5635,
             UserTypeGOOGLE = 5636,
+            RegisterINTEL = 5825,
+            MemoryINTEL = 5826,
+            NumbanksINTEL = 5827,
+            BankwidthINTEL = 5828,
+            MaxPrivateCopiesINTEL = 5829,
+            SinglepumpINTEL = 5830,
+            DoublepumpINTEL = 5831,
+            MaxReplicatesINTEL = 5832,
+            SimpleDualPortINTEL = 5833,
+            MergeINTEL = 5834,
+            BankBitsINTEL = 5835,
+            ForcePow2DepthINTEL = 5836,
         }
 
         public enum BuiltIn
@@ -629,6 +645,13 @@
             IterationMultiple = 6,
             PeelCount = 7,
             PartialCount = 8,
+            InitiationIntervalINTEL = 16,
+            MaxConcurrencyINTEL = 17,
+            DependencyArrayINTEL = 18,
+            PipelineEnableINTEL = 19,
+            LoopCoalesceINTEL = 20,
+            MaxInterleavingINTEL = 21,
+            SpeculatedIterationsINTEL = 22,
         }
 
         public enum LoopControlMask
@@ -643,6 +666,13 @@
             IterationMultiple = 0x00000040,
             PeelCount = 0x00000080,
             PartialCount = 0x00000100,
+            InitiationIntervalINTEL = 0x00010000,
+            MaxConcurrencyINTEL = 0x00020000,
+            DependencyArrayINTEL = 0x00040000,
+            PipelineEnableINTEL = 0x00080000,
+            LoopCoalesceINTEL = 0x00100000,
+            MaxInterleavingINTEL = 0x00200000,
+            SpeculatedIterationsINTEL = 0x00400000,
         }
 
         public enum FunctionControlShift
@@ -939,6 +969,13 @@
             SubgroupAvcMotionEstimationINTEL = 5696,
             SubgroupAvcMotionEstimationIntraINTEL = 5697,
             SubgroupAvcMotionEstimationChromaINTEL = 5698,
+            FPGAMemoryAttributesINTEL = 5824,
+            UnstructuredLoopControlsINTEL = 5886,
+            FPGALoopControlsINTEL = 5888,
+            KernelAttributesINTEL = 5892,
+            FPGAKernelAttributesINTEL = 5897,
+            BlockingPipesINTEL = 5945,
+            FPGARegINTEL = 5948,
         }
 
         public enum RayFlagsShift
@@ -1531,6 +1568,10 @@
             OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL = 5814,
             OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815,
             OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
+            OpLoopControlINTEL = 5887,
+            OpReadPipeBlockingINTEL = 5946,
+            OpWritePipeBlockingINTEL = 5947,
+            OpFPGARegINTEL = 5949,
             OpRayQueryGetRayTMinKHR = 6016,
             OpRayQueryGetRayFlagsKHR = 6017,
             OpRayQueryGetIntersectionTKHR = 6018,
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index 948c909..449d199 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -172,6 +172,10 @@
     SpvExecutionModeSampleInterlockUnorderedEXT = 5369,
     SpvExecutionModeShadingRateInterlockOrderedEXT = 5370,
     SpvExecutionModeShadingRateInterlockUnorderedEXT = 5371,
+    SpvExecutionModeMaxWorkgroupSizeINTEL = 5893,
+    SpvExecutionModeMaxWorkDimINTEL = 5894,
+    SpvExecutionModeNoGlobalOffsetINTEL = 5895,
+    SpvExecutionModeNumSIMDWorkitemsINTEL = 5896,
     SpvExecutionModeMax = 0x7fffffff,
 } SpvExecutionMode;
 
@@ -488,6 +492,18 @@
     SpvDecorationHlslSemanticGOOGLE = 5635,
     SpvDecorationUserSemantic = 5635,
     SpvDecorationUserTypeGOOGLE = 5636,
+    SpvDecorationRegisterINTEL = 5825,
+    SpvDecorationMemoryINTEL = 5826,
+    SpvDecorationNumbanksINTEL = 5827,
+    SpvDecorationBankwidthINTEL = 5828,
+    SpvDecorationMaxPrivateCopiesINTEL = 5829,
+    SpvDecorationSinglepumpINTEL = 5830,
+    SpvDecorationDoublepumpINTEL = 5831,
+    SpvDecorationMaxReplicatesINTEL = 5832,
+    SpvDecorationSimpleDualPortINTEL = 5833,
+    SpvDecorationMergeINTEL = 5834,
+    SpvDecorationBankBitsINTEL = 5835,
+    SpvDecorationForcePow2DepthINTEL = 5836,
     SpvDecorationMax = 0x7fffffff,
 } SpvDecoration;
 
@@ -634,6 +650,13 @@
     SpvLoopControlIterationMultipleShift = 6,
     SpvLoopControlPeelCountShift = 7,
     SpvLoopControlPartialCountShift = 8,
+    SpvLoopControlInitiationIntervalINTELShift = 16,
+    SpvLoopControlMaxConcurrencyINTELShift = 17,
+    SpvLoopControlDependencyArrayINTELShift = 18,
+    SpvLoopControlPipelineEnableINTELShift = 19,
+    SpvLoopControlLoopCoalesceINTELShift = 20,
+    SpvLoopControlMaxInterleavingINTELShift = 21,
+    SpvLoopControlSpeculatedIterationsINTELShift = 22,
     SpvLoopControlMax = 0x7fffffff,
 } SpvLoopControlShift;
 
@@ -648,6 +671,13 @@
     SpvLoopControlIterationMultipleMask = 0x00000040,
     SpvLoopControlPeelCountMask = 0x00000080,
     SpvLoopControlPartialCountMask = 0x00000100,
+    SpvLoopControlInitiationIntervalINTELMask = 0x00010000,
+    SpvLoopControlMaxConcurrencyINTELMask = 0x00020000,
+    SpvLoopControlDependencyArrayINTELMask = 0x00040000,
+    SpvLoopControlPipelineEnableINTELMask = 0x00080000,
+    SpvLoopControlLoopCoalesceINTELMask = 0x00100000,
+    SpvLoopControlMaxInterleavingINTELMask = 0x00200000,
+    SpvLoopControlSpeculatedIterationsINTELMask = 0x00400000,
 } SpvLoopControlMask;
 
 typedef enum SpvFunctionControlShift_ {
@@ -939,6 +969,13 @@
     SpvCapabilitySubgroupAvcMotionEstimationINTEL = 5696,
     SpvCapabilitySubgroupAvcMotionEstimationIntraINTEL = 5697,
     SpvCapabilitySubgroupAvcMotionEstimationChromaINTEL = 5698,
+    SpvCapabilityFPGAMemoryAttributesINTEL = 5824,
+    SpvCapabilityUnstructuredLoopControlsINTEL = 5886,
+    SpvCapabilityFPGALoopControlsINTEL = 5888,
+    SpvCapabilityKernelAttributesINTEL = 5892,
+    SpvCapabilityFPGAKernelAttributesINTEL = 5897,
+    SpvCapabilityBlockingPipesINTEL = 5945,
+    SpvCapabilityFPGARegINTEL = 5948,
     SpvCapabilityMax = 0x7fffffff,
 } SpvCapability;
 
@@ -1530,6 +1567,10 @@
     SpvOpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL = 5814,
     SpvOpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815,
     SpvOpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
+    SpvOpLoopControlINTEL = 5887,
+    SpvOpReadPipeBlockingINTEL = 5946,
+    SpvOpWritePipeBlockingINTEL = 5947,
+    SpvOpFPGARegINTEL = 5949,
     SpvOpRayQueryGetRayTMinKHR = 6016,
     SpvOpRayQueryGetRayFlagsKHR = 6017,
     SpvOpRayQueryGetIntersectionTKHR = 6018,
@@ -2087,6 +2128,10 @@
     case SpvOpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpSubgroupAvcSicGetInterRawSadsINTEL: *hasResult = true; *hasResultType = true; break;
+    case SpvOpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+    case SpvOpReadPipeBlockingINTEL: *hasResult = true; *hasResultType = true; break;
+    case SpvOpWritePipeBlockingINTEL: *hasResult = true; *hasResultType = true; break;
+    case SpvOpFPGARegINTEL: *hasResult = true; *hasResultType = true; break;
     case SpvOpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break;
     case SpvOpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break;
     case SpvOpRayQueryGetIntersectionTKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index fa89864..34c6d55 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -168,6 +168,10 @@
     ExecutionModeSampleInterlockUnorderedEXT = 5369,
     ExecutionModeShadingRateInterlockOrderedEXT = 5370,
     ExecutionModeShadingRateInterlockUnorderedEXT = 5371,
+    ExecutionModeMaxWorkgroupSizeINTEL = 5893,
+    ExecutionModeMaxWorkDimINTEL = 5894,
+    ExecutionModeNoGlobalOffsetINTEL = 5895,
+    ExecutionModeNumSIMDWorkitemsINTEL = 5896,
     ExecutionModeMax = 0x7fffffff,
 };
 
@@ -484,6 +488,18 @@
     DecorationHlslSemanticGOOGLE = 5635,
     DecorationUserSemantic = 5635,
     DecorationUserTypeGOOGLE = 5636,
+    DecorationRegisterINTEL = 5825,
+    DecorationMemoryINTEL = 5826,
+    DecorationNumbanksINTEL = 5827,
+    DecorationBankwidthINTEL = 5828,
+    DecorationMaxPrivateCopiesINTEL = 5829,
+    DecorationSinglepumpINTEL = 5830,
+    DecorationDoublepumpINTEL = 5831,
+    DecorationMaxReplicatesINTEL = 5832,
+    DecorationSimpleDualPortINTEL = 5833,
+    DecorationMergeINTEL = 5834,
+    DecorationBankBitsINTEL = 5835,
+    DecorationForcePow2DepthINTEL = 5836,
     DecorationMax = 0x7fffffff,
 };
 
@@ -630,6 +646,13 @@
     LoopControlIterationMultipleShift = 6,
     LoopControlPeelCountShift = 7,
     LoopControlPartialCountShift = 8,
+    LoopControlInitiationIntervalINTELShift = 16,
+    LoopControlMaxConcurrencyINTELShift = 17,
+    LoopControlDependencyArrayINTELShift = 18,
+    LoopControlPipelineEnableINTELShift = 19,
+    LoopControlLoopCoalesceINTELShift = 20,
+    LoopControlMaxInterleavingINTELShift = 21,
+    LoopControlSpeculatedIterationsINTELShift = 22,
     LoopControlMax = 0x7fffffff,
 };
 
@@ -644,6 +667,13 @@
     LoopControlIterationMultipleMask = 0x00000040,
     LoopControlPeelCountMask = 0x00000080,
     LoopControlPartialCountMask = 0x00000100,
+    LoopControlInitiationIntervalINTELMask = 0x00010000,
+    LoopControlMaxConcurrencyINTELMask = 0x00020000,
+    LoopControlDependencyArrayINTELMask = 0x00040000,
+    LoopControlPipelineEnableINTELMask = 0x00080000,
+    LoopControlLoopCoalesceINTELMask = 0x00100000,
+    LoopControlMaxInterleavingINTELMask = 0x00200000,
+    LoopControlSpeculatedIterationsINTELMask = 0x00400000,
 };
 
 enum FunctionControlShift {
@@ -935,6 +965,13 @@
     CapabilitySubgroupAvcMotionEstimationINTEL = 5696,
     CapabilitySubgroupAvcMotionEstimationIntraINTEL = 5697,
     CapabilitySubgroupAvcMotionEstimationChromaINTEL = 5698,
+    CapabilityFPGAMemoryAttributesINTEL = 5824,
+    CapabilityUnstructuredLoopControlsINTEL = 5886,
+    CapabilityFPGALoopControlsINTEL = 5888,
+    CapabilityKernelAttributesINTEL = 5892,
+    CapabilityFPGAKernelAttributesINTEL = 5897,
+    CapabilityBlockingPipesINTEL = 5945,
+    CapabilityFPGARegINTEL = 5948,
     CapabilityMax = 0x7fffffff,
 };
 
@@ -1526,6 +1563,10 @@
     OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL = 5814,
     OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815,
     OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
+    OpLoopControlINTEL = 5887,
+    OpReadPipeBlockingINTEL = 5946,
+    OpWritePipeBlockingINTEL = 5947,
+    OpFPGARegINTEL = 5949,
     OpRayQueryGetRayTMinKHR = 6016,
     OpRayQueryGetRayFlagsKHR = 6017,
     OpRayQueryGetIntersectionTKHR = 6018,
@@ -2083,6 +2124,10 @@
     case OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL: *hasResult = true; *hasResultType = true; break;
     case OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL: *hasResult = true; *hasResultType = true; break;
     case OpSubgroupAvcSicGetInterRawSadsINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+    case OpReadPipeBlockingINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpWritePipeBlockingINTEL: *hasResult = true; *hasResultType = true; break;
+    case OpFPGARegINTEL: *hasResult = true; *hasResultType = true; break;
     case OpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break;
     case OpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break;
     case OpRayQueryGetIntersectionTKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index 1835b76..b707160 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -168,6 +168,10 @@
     SampleInterlockUnorderedEXT = 5369,
     ShadingRateInterlockOrderedEXT = 5370,
     ShadingRateInterlockUnorderedEXT = 5371,
+    MaxWorkgroupSizeINTEL = 5893,
+    MaxWorkDimINTEL = 5894,
+    NoGlobalOffsetINTEL = 5895,
+    NumSIMDWorkitemsINTEL = 5896,
     Max = 0x7fffffff,
 };
 
@@ -484,6 +488,18 @@
     HlslSemanticGOOGLE = 5635,
     UserSemantic = 5635,
     UserTypeGOOGLE = 5636,
+    RegisterINTEL = 5825,
+    MemoryINTEL = 5826,
+    NumbanksINTEL = 5827,
+    BankwidthINTEL = 5828,
+    MaxPrivateCopiesINTEL = 5829,
+    SinglepumpINTEL = 5830,
+    DoublepumpINTEL = 5831,
+    MaxReplicatesINTEL = 5832,
+    SimpleDualPortINTEL = 5833,
+    MergeINTEL = 5834,
+    BankBitsINTEL = 5835,
+    ForcePow2DepthINTEL = 5836,
     Max = 0x7fffffff,
 };
 
@@ -630,6 +646,13 @@
     IterationMultiple = 6,
     PeelCount = 7,
     PartialCount = 8,
+    InitiationIntervalINTEL = 16,
+    MaxConcurrencyINTEL = 17,
+    DependencyArrayINTEL = 18,
+    PipelineEnableINTEL = 19,
+    LoopCoalesceINTEL = 20,
+    MaxInterleavingINTEL = 21,
+    SpeculatedIterationsINTEL = 22,
     Max = 0x7fffffff,
 };
 
@@ -644,6 +667,13 @@
     IterationMultiple = 0x00000040,
     PeelCount = 0x00000080,
     PartialCount = 0x00000100,
+    InitiationIntervalINTEL = 0x00010000,
+    MaxConcurrencyINTEL = 0x00020000,
+    DependencyArrayINTEL = 0x00040000,
+    PipelineEnableINTEL = 0x00080000,
+    LoopCoalesceINTEL = 0x00100000,
+    MaxInterleavingINTEL = 0x00200000,
+    SpeculatedIterationsINTEL = 0x00400000,
 };
 
 enum class FunctionControlShift : unsigned {
@@ -935,6 +965,13 @@
     SubgroupAvcMotionEstimationINTEL = 5696,
     SubgroupAvcMotionEstimationIntraINTEL = 5697,
     SubgroupAvcMotionEstimationChromaINTEL = 5698,
+    FPGAMemoryAttributesINTEL = 5824,
+    UnstructuredLoopControlsINTEL = 5886,
+    FPGALoopControlsINTEL = 5888,
+    KernelAttributesINTEL = 5892,
+    FPGAKernelAttributesINTEL = 5897,
+    BlockingPipesINTEL = 5945,
+    FPGARegINTEL = 5948,
     Max = 0x7fffffff,
 };
 
@@ -1526,6 +1563,10 @@
     OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL = 5814,
     OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815,
     OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
+    OpLoopControlINTEL = 5887,
+    OpReadPipeBlockingINTEL = 5946,
+    OpWritePipeBlockingINTEL = 5947,
+    OpFPGARegINTEL = 5949,
     OpRayQueryGetRayTMinKHR = 6016,
     OpRayQueryGetRayFlagsKHR = 6017,
     OpRayQueryGetIntersectionTKHR = 6018,
@@ -2083,6 +2124,10 @@
     case Op::OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpSubgroupAvcSicGetInterRawSadsINTEL: *hasResult = true; *hasResultType = true; break;
+    case Op::OpLoopControlINTEL: *hasResult = false; *hasResultType = false; break;
+    case Op::OpReadPipeBlockingINTEL: *hasResult = true; *hasResultType = true; break;
+    case Op::OpWritePipeBlockingINTEL: *hasResult = true; *hasResultType = true; break;
+    case Op::OpFPGARegINTEL: *hasResult = true; *hasResultType = true; break;
     case Op::OpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break;
     case Op::OpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break;
     case Op::OpRayQueryGetIntersectionTKHR: *hasResult = true; *hasResultType = true; break;
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index 8f69b83..25c1901 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -186,7 +186,11 @@
                     "SampleInterlockOrderedEXT": 5368,
                     "SampleInterlockUnorderedEXT": 5369,
                     "ShadingRateInterlockOrderedEXT": 5370,
-                    "ShadingRateInterlockUnorderedEXT": 5371
+                    "ShadingRateInterlockUnorderedEXT": 5371,
+                    "MaxWorkgroupSizeINTEL": 5893,
+                    "MaxWorkDimINTEL": 5894,
+                    "NoGlobalOffsetINTEL": 5895,
+                    "NumSIMDWorkitemsINTEL": 5896
                 }
             },
             {
@@ -513,7 +517,19 @@
                     "HlslCounterBufferGOOGLE": 5634,
                     "HlslSemanticGOOGLE": 5635,
                     "UserSemantic": 5635,
-                    "UserTypeGOOGLE": 5636
+                    "UserTypeGOOGLE": 5636,
+                    "RegisterINTEL": 5825,
+                    "MemoryINTEL": 5826,
+                    "NumbanksINTEL": 5827,
+                    "BankwidthINTEL": 5828,
+                    "MaxPrivateCopiesINTEL": 5829,
+                    "SinglepumpINTEL": 5830,
+                    "DoublepumpINTEL": 5831,
+                    "MaxReplicatesINTEL": 5832,
+                    "SimpleDualPortINTEL": 5833,
+                    "MergeINTEL": 5834,
+                    "BankBitsINTEL": 5835,
+                    "ForcePow2DepthINTEL": 5836
                 }
             },
             {
@@ -662,7 +678,14 @@
                     "MaxIterations": 5,
                     "IterationMultiple": 6,
                     "PeelCount": 7,
-                    "PartialCount": 8
+                    "PartialCount": 8,
+                    "InitiationIntervalINTEL": 16,
+                    "MaxConcurrencyINTEL": 17,
+                    "DependencyArrayINTEL": 18,
+                    "PipelineEnableINTEL": 19,
+                    "LoopCoalesceINTEL": 20,
+                    "MaxInterleavingINTEL": 21,
+                    "SpeculatedIterationsINTEL": 22
                 }
             },
             {
@@ -931,7 +954,14 @@
                     "IndirectReferencesINTEL": 5604,
                     "SubgroupAvcMotionEstimationINTEL": 5696,
                     "SubgroupAvcMotionEstimationIntraINTEL": 5697,
-                    "SubgroupAvcMotionEstimationChromaINTEL": 5698
+                    "SubgroupAvcMotionEstimationChromaINTEL": 5698,
+                    "FPGAMemoryAttributesINTEL": 5824,
+                    "UnstructuredLoopControlsINTEL": 5886,
+                    "FPGALoopControlsINTEL": 5888,
+                    "KernelAttributesINTEL": 5892,
+                    "FPGAKernelAttributesINTEL": 5897,
+                    "BlockingPipesINTEL": 5945,
+                    "FPGARegINTEL": 5948
                 }
             },
             {
@@ -1524,6 +1554,10 @@
                     "OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL": 5814,
                     "OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL": 5815,
                     "OpSubgroupAvcSicGetInterRawSadsINTEL": 5816,
+                    "OpLoopControlINTEL": 5887,
+                    "OpReadPipeBlockingINTEL": 5946,
+                    "OpWritePipeBlockingINTEL": 5947,
+                    "OpFPGARegINTEL": 5949,
                     "OpRayQueryGetRayTMinKHR": 6016,
                     "OpRayQueryGetRayFlagsKHR": 6017,
                     "OpRayQueryGetIntersectionTKHR": 6018,
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index cf41934..6f35225 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -155,6 +155,10 @@
         SampleInterlockUnorderedEXT = 5369,
         ShadingRateInterlockOrderedEXT = 5370,
         ShadingRateInterlockUnorderedEXT = 5371,
+        MaxWorkgroupSizeINTEL = 5893,
+        MaxWorkDimINTEL = 5894,
+        NoGlobalOffsetINTEL = 5895,
+        NumSIMDWorkitemsINTEL = 5896,
     },
 
     StorageClass = {
@@ -457,6 +461,18 @@
         HlslSemanticGOOGLE = 5635,
         UserSemantic = 5635,
         UserTypeGOOGLE = 5636,
+        RegisterINTEL = 5825,
+        MemoryINTEL = 5826,
+        NumbanksINTEL = 5827,
+        BankwidthINTEL = 5828,
+        MaxPrivateCopiesINTEL = 5829,
+        SinglepumpINTEL = 5830,
+        DoublepumpINTEL = 5831,
+        MaxReplicatesINTEL = 5832,
+        SimpleDualPortINTEL = 5833,
+        MergeINTEL = 5834,
+        BankBitsINTEL = 5835,
+        ForcePow2DepthINTEL = 5836,
     },
 
     BuiltIn = {
@@ -600,6 +616,13 @@
         IterationMultiple = 6,
         PeelCount = 7,
         PartialCount = 8,
+        InitiationIntervalINTEL = 16,
+        MaxConcurrencyINTEL = 17,
+        DependencyArrayINTEL = 18,
+        PipelineEnableINTEL = 19,
+        LoopCoalesceINTEL = 20,
+        MaxInterleavingINTEL = 21,
+        SpeculatedIterationsINTEL = 22,
     },
 
     LoopControlMask = {
@@ -613,6 +636,13 @@
         IterationMultiple = 0x00000040,
         PeelCount = 0x00000080,
         PartialCount = 0x00000100,
+        InitiationIntervalINTEL = 0x00010000,
+        MaxConcurrencyINTEL = 0x00020000,
+        DependencyArrayINTEL = 0x00040000,
+        PipelineEnableINTEL = 0x00080000,
+        LoopCoalesceINTEL = 0x00100000,
+        MaxInterleavingINTEL = 0x00200000,
+        SpeculatedIterationsINTEL = 0x00400000,
     },
 
     FunctionControlShift = {
@@ -897,6 +927,13 @@
         SubgroupAvcMotionEstimationINTEL = 5696,
         SubgroupAvcMotionEstimationIntraINTEL = 5697,
         SubgroupAvcMotionEstimationChromaINTEL = 5698,
+        FPGAMemoryAttributesINTEL = 5824,
+        UnstructuredLoopControlsINTEL = 5886,
+        FPGALoopControlsINTEL = 5888,
+        KernelAttributesINTEL = 5892,
+        FPGAKernelAttributesINTEL = 5897,
+        BlockingPipesINTEL = 5945,
+        FPGARegINTEL = 5948,
     },
 
     RayFlagsShift = {
@@ -1483,6 +1520,10 @@
         OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL = 5814,
         OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815,
         OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
+        OpLoopControlINTEL = 5887,
+        OpReadPipeBlockingINTEL = 5946,
+        OpWritePipeBlockingINTEL = 5947,
+        OpFPGARegINTEL = 5949,
         OpRayQueryGetRayTMinKHR = 6016,
         OpRayQueryGetRayFlagsKHR = 6017,
         OpRayQueryGetIntersectionTKHR = 6018,
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index f6dda3d..4a32b29 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -155,6 +155,10 @@
         'SampleInterlockUnorderedEXT' : 5369,
         'ShadingRateInterlockOrderedEXT' : 5370,
         'ShadingRateInterlockUnorderedEXT' : 5371,
+        'MaxWorkgroupSizeINTEL' : 5893,
+        'MaxWorkDimINTEL' : 5894,
+        'NoGlobalOffsetINTEL' : 5895,
+        'NumSIMDWorkitemsINTEL' : 5896,
     },
 
     'StorageClass' : {
@@ -457,6 +461,18 @@
         'HlslSemanticGOOGLE' : 5635,
         'UserSemantic' : 5635,
         'UserTypeGOOGLE' : 5636,
+        'RegisterINTEL' : 5825,
+        'MemoryINTEL' : 5826,
+        'NumbanksINTEL' : 5827,
+        'BankwidthINTEL' : 5828,
+        'MaxPrivateCopiesINTEL' : 5829,
+        'SinglepumpINTEL' : 5830,
+        'DoublepumpINTEL' : 5831,
+        'MaxReplicatesINTEL' : 5832,
+        'SimpleDualPortINTEL' : 5833,
+        'MergeINTEL' : 5834,
+        'BankBitsINTEL' : 5835,
+        'ForcePow2DepthINTEL' : 5836,
     },
 
     'BuiltIn' : {
@@ -600,6 +616,13 @@
         'IterationMultiple' : 6,
         'PeelCount' : 7,
         'PartialCount' : 8,
+        'InitiationIntervalINTEL' : 16,
+        'MaxConcurrencyINTEL' : 17,
+        'DependencyArrayINTEL' : 18,
+        'PipelineEnableINTEL' : 19,
+        'LoopCoalesceINTEL' : 20,
+        'MaxInterleavingINTEL' : 21,
+        'SpeculatedIterationsINTEL' : 22,
     },
 
     'LoopControlMask' : {
@@ -613,6 +636,13 @@
         'IterationMultiple' : 0x00000040,
         'PeelCount' : 0x00000080,
         'PartialCount' : 0x00000100,
+        'InitiationIntervalINTEL' : 0x00010000,
+        'MaxConcurrencyINTEL' : 0x00020000,
+        'DependencyArrayINTEL' : 0x00040000,
+        'PipelineEnableINTEL' : 0x00080000,
+        'LoopCoalesceINTEL' : 0x00100000,
+        'MaxInterleavingINTEL' : 0x00200000,
+        'SpeculatedIterationsINTEL' : 0x00400000,
     },
 
     'FunctionControlShift' : {
@@ -897,6 +927,13 @@
         'SubgroupAvcMotionEstimationINTEL' : 5696,
         'SubgroupAvcMotionEstimationIntraINTEL' : 5697,
         'SubgroupAvcMotionEstimationChromaINTEL' : 5698,
+        'FPGAMemoryAttributesINTEL' : 5824,
+        'UnstructuredLoopControlsINTEL' : 5886,
+        'FPGALoopControlsINTEL' : 5888,
+        'KernelAttributesINTEL' : 5892,
+        'FPGAKernelAttributesINTEL' : 5897,
+        'BlockingPipesINTEL' : 5945,
+        'FPGARegINTEL' : 5948,
     },
 
     'RayFlagsShift' : {
@@ -1483,6 +1520,10 @@
         'OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL' : 5814,
         'OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL' : 5815,
         'OpSubgroupAvcSicGetInterRawSadsINTEL' : 5816,
+        'OpLoopControlINTEL' : 5887,
+        'OpReadPipeBlockingINTEL' : 5946,
+        'OpWritePipeBlockingINTEL' : 5947,
+        'OpFPGARegINTEL' : 5949,
         'OpRayQueryGetRayTMinKHR' : 6016,
         'OpRayQueryGetRayFlagsKHR' : 6017,
         'OpRayQueryGetIntersectionTKHR' : 6018,
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index 9a2ae69..8714d0e 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -167,6 +167,10 @@
     SampleInterlockUnorderedEXT = 5369,
     ShadingRateInterlockOrderedEXT = 5370,
     ShadingRateInterlockUnorderedEXT = 5371,
+    MaxWorkgroupSizeINTEL = 5893,
+    MaxWorkDimINTEL = 5894,
+    NoGlobalOffsetINTEL = 5895,
+    NumSIMDWorkitemsINTEL = 5896,
 }
 
 enum StorageClass : uint
@@ -485,6 +489,18 @@
     HlslSemanticGOOGLE = 5635,
     UserSemantic = 5635,
     UserTypeGOOGLE = 5636,
+    RegisterINTEL = 5825,
+    MemoryINTEL = 5826,
+    NumbanksINTEL = 5827,
+    BankwidthINTEL = 5828,
+    MaxPrivateCopiesINTEL = 5829,
+    SinglepumpINTEL = 5830,
+    DoublepumpINTEL = 5831,
+    MaxReplicatesINTEL = 5832,
+    SimpleDualPortINTEL = 5833,
+    MergeINTEL = 5834,
+    BankBitsINTEL = 5835,
+    ForcePow2DepthINTEL = 5836,
 }
 
 enum BuiltIn : uint
@@ -632,6 +648,13 @@
     IterationMultiple = 6,
     PeelCount = 7,
     PartialCount = 8,
+    InitiationIntervalINTEL = 16,
+    MaxConcurrencyINTEL = 17,
+    DependencyArrayINTEL = 18,
+    PipelineEnableINTEL = 19,
+    LoopCoalesceINTEL = 20,
+    MaxInterleavingINTEL = 21,
+    SpeculatedIterationsINTEL = 22,
 }
 
 enum LoopControlMask : uint
@@ -646,6 +669,13 @@
     IterationMultiple = 0x00000040,
     PeelCount = 0x00000080,
     PartialCount = 0x00000100,
+    InitiationIntervalINTEL = 0x00010000,
+    MaxConcurrencyINTEL = 0x00020000,
+    DependencyArrayINTEL = 0x00040000,
+    PipelineEnableINTEL = 0x00080000,
+    LoopCoalesceINTEL = 0x00100000,
+    MaxInterleavingINTEL = 0x00200000,
+    SpeculatedIterationsINTEL = 0x00400000,
 }
 
 enum FunctionControlShift : uint
@@ -942,6 +972,13 @@
     SubgroupAvcMotionEstimationINTEL = 5696,
     SubgroupAvcMotionEstimationIntraINTEL = 5697,
     SubgroupAvcMotionEstimationChromaINTEL = 5698,
+    FPGAMemoryAttributesINTEL = 5824,
+    UnstructuredLoopControlsINTEL = 5886,
+    FPGALoopControlsINTEL = 5888,
+    KernelAttributesINTEL = 5892,
+    FPGAKernelAttributesINTEL = 5897,
+    BlockingPipesINTEL = 5945,
+    FPGARegINTEL = 5948,
 }
 
 enum RayFlagsShift : uint
@@ -1534,6 +1571,10 @@
     OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL = 5814,
     OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815,
     OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
+    OpLoopControlINTEL = 5887,
+    OpReadPipeBlockingINTEL = 5946,
+    OpWritePipeBlockingINTEL = 5947,
+    OpFPGARegINTEL = 5949,
     OpRayQueryGetRayTMinKHR = 6016,
     OpRayQueryGetRayFlagsKHR = 6017,
     OpRayQueryGetIntersectionTKHR = 6018,